Register scavenger is now capable of scavenging. It spills a register whose use of...

[oota-llvm.git] / include / llvm / CodeGen / SelectionDAGISel.h

diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h
index f439f21d6fa8b06db9e86ffc1b0f52524bbcf883..492e877f192ad828bc3458c4d0bdb3760bf77259 100644 (file)
--- a/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/include/llvm/CodeGen/SelectionDAGISel.h
@@ -31,6 +31,20 @@ namespace llvm {
   class FunctionLoweringInfo;
   class HazardRecognizer;
 
+  namespace SDISelParamFlags {
+    enum Flags {
+      NoFlagSet         = 0,
+      Signed            = 1<<0,
+      SignedOffs        = 0,
+      InReg             = 1<<1,
+      InRegOffs         = 1,
+      StructReturn      = 1<<2,
+      StructReturnOffs  = 2,
+      OrigAlignment     = 0x1F<<27,
+      OrigAlignmentOffs = 27
+    };
+  }
+  
 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
 /// pattern-matching instruction selectors.
 class SelectionDAGISel : public FunctionPass {
@@ -71,8 +85,8 @@ public:
   }
 
   /// CanBeFoldedBy - Returns true if the specific operand node N of U can be
-  /// folded during instruction selection?
-  virtual bool CanBeFoldedBy(SDNode *N, SDNode *U) { return true; }
+  /// folded during instruction selection that starts at Root?
+  virtual bool CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) { return true;}
   
   /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
   /// to use for this target when scheduling the DAG.
@@ -82,20 +96,18 @@ public:
   /// SDISel for the code generation of additional basic blocks needed by multi-
   /// case switch statements.
   struct CaseBlock {
-    CaseBlock(ISD::CondCode cc, Value *s, Constant *c, MachineBasicBlock *lhs,
-              MachineBasicBlock *rhs, MachineBasicBlock *me) : 
-    CC(cc), SwitchV(s), CaseC(c), LHSBB(lhs), RHSBB(rhs), ThisBB(me) {}
+    CaseBlock(ISD::CondCode cc, Value *cmplhs, Value *cmprhs, 
+              MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
+              MachineBasicBlock *me)
+      : CC(cc), CmpLHS(cmplhs), CmpRHS(cmprhs),
+        TrueBB(truebb), FalseBB(falsebb), ThisBB(me) {}
     // CC - the condition code to use for the case block's setcc node
     ISD::CondCode CC;
-    // SwitchV - the value to be switched on, 'foo' in switch(foo)
-    Value *SwitchV;
-    // CaseC - the constant the setcc node will compare against SwitchV
-    Constant *CaseC;
-    // LHSBB - the block to branch to if the setcc is true
-    MachineBasicBlock *LHSBB;
-    // RHSBB - the block to branch to if the setcc is false
-    MachineBasicBlock *RHSBB;
-    // ThisBB - the blcok into which to emit the code for the setcc and branches
+    // CmpLHS/CmpRHS - The LHS/RHS of the comparison to emit.
+    Value *CmpLHS, *CmpRHS;
+    // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
+    MachineBasicBlock *TrueBB, *FalseBB;
+    // ThisBB - the block into which to emit the code for the setcc and branches
     MachineBasicBlock *ThisBB;
   };
   struct JumpTable {
@@ -123,9 +135,11 @@ protected:
   void SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops,
                                      SelectionDAG &DAG);
 
+  // Calls to these predicates are generated by tblgen.
+  bool CheckAndMask(SDOperand LHS, ConstantSDNode *RHS, int64_t DesiredMaskS);  
+  bool CheckOrMask(SDOperand LHS, ConstantSDNode *RHS, int64_t DesiredMaskS);  
+  
 private:
-  SDOperand CopyValueToVirtualRegister(SelectionDAGLowering &SDL,
-                                       Value *V, unsigned Reg);
   void SelectBasicBlock(BasicBlock *BB, MachineFunction &MF,
                         FunctionLoweringInfo &FuncInfo);