//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
namespace llvm {
class SelectionDAGLowering;
class SDOperand;
- class SSARegMap;
+ class MachineRegisterInfo;
class MachineBasicBlock;
class MachineFunction;
class MachineInstr;
class TargetLowering;
class FunctionLoweringInfo;
class HazardRecognizer;
-
+ class CollectorMetadata;
+
/// SelectionDAGISel - This is the common base class used for SelectionDAG-based
/// pattern-matching instruction selectors.
class SelectionDAGISel : public FunctionPass {
public:
TargetLowering &TLI;
- SSARegMap *RegMap;
+ MachineRegisterInfo *RegInfo;
SelectionDAG *CurDAG;
MachineBasicBlock *BB;
+ AliasAnalysis *AA;
std::vector<SDNode*> TopOrder;
unsigned DAGSize;
+ CollectorMetadata *GCI;
+ static char ID;
- SelectionDAGISel(TargetLowering &tli) : TLI(tli), DAGSize(0), JT(0,0,0,0) {}
+ explicit SelectionDAGISel(TargetLowering &tli) :
+ FunctionPass((intptr_t)&ID), TLI(tli), DAGSize(0), GCI(0) {}
TargetLowering &getTargetLowering() { return TLI; }
}
/// CanBeFoldedBy - Returns true if the specific operand node N of U can be
- /// folded during instruction selection?
- virtual bool CanBeFoldedBy(SDNode *N, SDNode *U) { return true; }
+ /// folded during instruction selection that starts at Root?
+ virtual bool CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) const {
+ return true;
+ }
/// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
/// to use for this target when scheduling the DAG.
/// SDISel for the code generation of additional basic blocks needed by multi-
/// case switch statements.
struct CaseBlock {
- CaseBlock(ISD::CondCode cc, Value *s, Constant *c, MachineBasicBlock *lhs,
- MachineBasicBlock *rhs, MachineBasicBlock *me) :
- CC(cc), SwitchV(s), CaseC(c), LHSBB(lhs), RHSBB(rhs), ThisBB(me) {}
+ CaseBlock(ISD::CondCode cc, Value *cmplhs, Value *cmprhs, Value *cmpmiddle,
+ MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
+ MachineBasicBlock *me)
+ : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
+ TrueBB(truebb), FalseBB(falsebb), ThisBB(me) {}
// CC - the condition code to use for the case block's setcc node
ISD::CondCode CC;
- // SwitchV - the value to be switched on, 'foo' in switch(foo)
- Value *SwitchV;
- // CaseC - the constant the setcc node will compare against SwitchV
- Constant *CaseC;
- // LHSBB - the block to branch to if the setcc is true
- MachineBasicBlock *LHSBB;
- // RHSBB - the block to branch to if the setcc is false
- MachineBasicBlock *RHSBB;
- // ThisBB - the blcok into which to emit the code for the setcc and branches
+ // CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
+ // Emit by default LHS op RHS. MHS is used for range comparisons:
+ // If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
+ Value *CmpLHS, *CmpMHS, *CmpRHS;
+ // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
+ MachineBasicBlock *TrueBB, *FalseBB;
+ // ThisBB - the block into which to emit the code for the setcc and branches
MachineBasicBlock *ThisBB;
};
struct JumpTable {
JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
- MachineBasicBlock *D) : Reg(R), JTI(J), MBB(M), Default(D) {}
- // Reg - the virtual register containing the index of the jump table entry
- // to jump to.
+ MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
+
+ /// Reg - the virtual register containing the index of the jump table entry
+ //. to jump to.
unsigned Reg;
- // JTI - the JumpTableIndex for this jump table in the function.
+ /// JTI - the JumpTableIndex for this jump table in the function.
unsigned JTI;
- // MBB - the MBB into which to emit the code for the indirect jump.
+ /// MBB - the MBB into which to emit the code for the indirect jump.
MachineBasicBlock *MBB;
- // Default - the MBB of the default bb, which is a successor of the range
- // check MBB. This is when updating PHI nodes in successors.
+ /// Default - the MBB of the default bb, which is a successor of the range
+ /// check MBB. This is when updating PHI nodes in successors.
MachineBasicBlock *Default;
};
+ struct JumpTableHeader {
+ JumpTableHeader(uint64_t F, uint64_t L, Value* SV, MachineBasicBlock* H,
+ bool E = false):
+ First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
+ uint64_t First;
+ uint64_t Last;
+ Value *SValue;
+ MachineBasicBlock *HeaderBB;
+ bool Emitted;
+ };
+ typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
+
+ struct BitTestCase {
+ BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr):
+ Mask(M), ThisBB(T), TargetBB(Tr) { }
+ uint64_t Mask;
+ MachineBasicBlock* ThisBB;
+ MachineBasicBlock* TargetBB;
+ };
+ typedef SmallVector<BitTestCase, 3> BitTestInfo;
+
+ struct BitTestBlock {
+ BitTestBlock(uint64_t F, uint64_t R, Value* SV,
+ unsigned Rg, bool E,
+ MachineBasicBlock* P, MachineBasicBlock* D,
+ const BitTestInfo& C):
+ First(F), Range(R), SValue(SV), Reg(Rg), Emitted(E),
+ Parent(P), Default(D), Cases(C) { }
+ uint64_t First;
+ uint64_t Range;
+ Value *SValue;
+ unsigned Reg;
+ bool Emitted;
+ MachineBasicBlock *Parent;
+ MachineBasicBlock *Default;
+ BitTestInfo Cases;
+ };
protected:
/// Pick a safe ordering and emit instructions for each target node in the
/// graph.
void SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops,
SelectionDAG &DAG);
+ // Calls to these predicates are generated by tblgen.
+ bool CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
+ int64_t DesiredMaskS) const;
+ bool CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
+ int64_t DesiredMaskS) const;
+
private:
- SDOperand CopyValueToVirtualRegister(SelectionDAGLowering &SDL,
- Value *V, unsigned Reg);
void SelectBasicBlock(BasicBlock *BB, MachineFunction &MF,
FunctionLoweringInfo &FuncInfo);
/// SwitchInst code generation information.
std::vector<CaseBlock> SwitchCases;
- /// JT - Record which holds necessary information for emitting a jump table
- JumpTable JT;
+ /// JTCases - Vector of JumpTable structures which holds necessary information
+ /// for emitting a jump tables during SwitchInst code generation.
+ std::vector<JumpTableBlock> JTCases;
+
+ std::vector<BitTestBlock> BitTestCases;
};
}
projects / oota-llvm.git / blobdiff