//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
namespace llvm {
class SelectionDAGLowering;
class SDOperand;
- class SSARegMap;
+ class MachineRegisterInfo;
class MachineBasicBlock;
class MachineFunction;
class MachineInstr;
class TargetLowering;
class FunctionLoweringInfo;
class HazardRecognizer;
+ class CollectorMetadata;
/// SelectionDAGISel - This is the common base class used for SelectionDAG-based
/// pattern-matching instruction selectors.
class SelectionDAGISel : public FunctionPass {
public:
TargetLowering &TLI;
- SSARegMap *RegMap;
+ MachineRegisterInfo *RegInfo;
SelectionDAG *CurDAG;
MachineBasicBlock *BB;
+ AliasAnalysis *AA;
std::vector<SDNode*> TopOrder;
unsigned DAGSize;
+ CollectorMetadata *GCI;
+ static char ID;
- explicit SelectionDAGISel(TargetLowering &tli) : TLI(tli), DAGSize(0) {}
+ explicit SelectionDAGISel(TargetLowering &tli) :
+ FunctionPass((intptr_t)&ID), TLI(tli), DAGSize(0), GCI(0) {}
TargetLowering &getTargetLowering() { return TLI; }
/// CanBeFoldedBy - Returns true if the specific operand node N of U can be
/// folded during instruction selection that starts at Root?
- virtual bool CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) { return true;}
+ virtual bool CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) const {
+ return true;
+ }
/// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
/// to use for this target when scheduling the DAG.
};
struct JumpTable {
JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
- MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {};
+ MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
/// Reg - the virtual register containing the index of the jump table entry
//. to jump to.
struct JumpTableHeader {
JumpTableHeader(uint64_t F, uint64_t L, Value* SV, MachineBasicBlock* H,
bool E = false):
- First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {};
+ First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
uint64_t First;
uint64_t Last;
Value *SValue;
bool Emitted;
};
typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
-
+
+ struct BitTestCase {
+ BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr):
+ Mask(M), ThisBB(T), TargetBB(Tr) { }
+ uint64_t Mask;
+ MachineBasicBlock* ThisBB;
+ MachineBasicBlock* TargetBB;
+ };
+
+ typedef SmallVector<BitTestCase, 3> BitTestInfo;
+
+ struct BitTestBlock {
+ BitTestBlock(uint64_t F, uint64_t R, Value* SV,
+ unsigned Rg, bool E,
+ MachineBasicBlock* P, MachineBasicBlock* D,
+ const BitTestInfo& C):
+ First(F), Range(R), SValue(SV), Reg(Rg), Emitted(E),
+ Parent(P), Default(D), Cases(C) { }
+ uint64_t First;
+ uint64_t Range;
+ Value *SValue;
+ unsigned Reg;
+ bool Emitted;
+ MachineBasicBlock *Parent;
+ MachineBasicBlock *Default;
+ BitTestInfo Cases;
+ };
protected:
/// Pick a safe ordering and emit instructions for each target node in the
/// graph.
SelectionDAG &DAG);
// Calls to these predicates are generated by tblgen.
- bool CheckAndMask(SDOperand LHS, ConstantSDNode *RHS, int64_t DesiredMaskS);
- bool CheckOrMask(SDOperand LHS, ConstantSDNode *RHS, int64_t DesiredMaskS);
+ bool CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
+ int64_t DesiredMaskS) const;
+ bool CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
+ int64_t DesiredMaskS) const;
private:
void SelectBasicBlock(BasicBlock *BB, MachineFunction &MF,
/// JTCases - Vector of JumpTable structures which holds necessary information
/// for emitting a jump tables during SwitchInst code generation.
std::vector<JumpTableBlock> JTCases;
+
+ std::vector<BitTestBlock> BitTestCases;
};
}