Fix comment.

[oota-llvm.git] / include / llvm / CodeGen / SelectionDAGISel.h

diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h
index 790f23ba6b002fb547befe1881aeebb75a931cb1..8557702018f764ce689caa03952d7177c9abc597 100644 (file)
--- a/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/include/llvm/CodeGen/SelectionDAGISel.h
@@ -17,10 +17,10 @@
 
 #include "llvm/Pass.h"
 #include "llvm/Constant.h"
+#include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/SelectionDAGNodes.h"
 
 namespace llvm {
-  class SelectionDAG;
   class SelectionDAGLowering;
   class SDOperand;
   class SSARegMap;
@@ -30,7 +30,7 @@ namespace llvm {
   class TargetLowering;
   class FunctionLoweringInfo;
   class HazardRecognizer;
-
+ 
 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
 /// pattern-matching instruction selectors.
 class SelectionDAGISel : public FunctionPass {
@@ -39,8 +39,12 @@ public:
   SSARegMap *RegMap;
   SelectionDAG *CurDAG;
   MachineBasicBlock *BB;
+  std::vector<SDNode*> TopOrder;
+  unsigned DAGSize;
 
-  SelectionDAGISel(TargetLowering &tli) : TLI(tli), JT(0,0,0,0) {}
+  SelectionDAGISel(TargetLowering &tli) : TLI(tli), DAGSize(0), JT(0,0,0,0) {}
+  
+  TargetLowering &getTargetLowering() { return TLI; }
 
   virtual void getAnalysisUsage(AnalysisUsage &AU) const;
 
@@ -50,6 +54,9 @@ public:
 
   virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
   virtual void InstructionSelectBasicBlock(SelectionDAG &SD) = 0;
+  virtual void SelectRootInit() {
+    DAGSize = CurDAG->AssignTopologicalOrder(TopOrder);
+  }
 
   /// SelectInlineAsmMemoryOperand - Select the specified address as a target
   /// addressing mode, according to the specified constraint code.  If this does
@@ -63,9 +70,9 @@ public:
     return true;
   }
 
-  /// IsFoldableBy - Returns true if the specific operand node N of U can be
-  /// folded during instruction selection?
-  virtual bool IsFoldableBy(SDNode *N, SDNode *U) { return true; }
+  /// CanBeFoldedBy - Returns true if the specific operand node N of U can be
+  /// folded during instruction selection that starts at Root?
+  virtual bool CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) { return true;}
   
   /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
   /// to use for this target when scheduling the DAG.
@@ -75,20 +82,18 @@ public:
   /// SDISel for the code generation of additional basic blocks needed by multi-
   /// case switch statements.
   struct CaseBlock {
-    CaseBlock(ISD::CondCode cc, Value *s, Constant *c, MachineBasicBlock *lhs,
-              MachineBasicBlock *rhs, MachineBasicBlock *me) : 
-    CC(cc), SwitchV(s), CaseC(c), LHSBB(lhs), RHSBB(rhs), ThisBB(me) {}
+    CaseBlock(ISD::CondCode cc, Value *cmplhs, Value *cmprhs, 
+              MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
+              MachineBasicBlock *me)
+      : CC(cc), CmpLHS(cmplhs), CmpRHS(cmprhs),
+        TrueBB(truebb), FalseBB(falsebb), ThisBB(me) {}
     // CC - the condition code to use for the case block's setcc node
     ISD::CondCode CC;
-    // SwitchV - the value to be switched on, 'foo' in switch(foo)
-    Value *SwitchV;
-    // CaseC - the constant the setcc node will compare against SwitchV
-    Constant *CaseC;
-    // LHSBB - the block to branch to if the setcc is true
-    MachineBasicBlock *LHSBB;
-    // RHSBB - the block to branch to if the setcc is false
-    MachineBasicBlock *RHSBB;
-    // ThisBB - the blcok into which to emit the code for the setcc and branches
+    // CmpLHS/CmpRHS - The LHS/RHS of the comparison to emit.
+    Value *CmpLHS, *CmpRHS;
+    // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
+    MachineBasicBlock *TrueBB, *FalseBB;
+    // ThisBB - the block into which to emit the code for the setcc and branches
     MachineBasicBlock *ThisBB;
   };
   struct JumpTable {
@@ -116,9 +121,11 @@ protected:
   void SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops,
                                      SelectionDAG &DAG);
 
+  // Calls to these predicates are generated by tblgen.
+  bool CheckAndMask(SDOperand LHS, ConstantSDNode *RHS, int64_t DesiredMaskS);  
+  bool CheckOrMask(SDOperand LHS, ConstantSDNode *RHS, int64_t DesiredMaskS);  
+  
 private:
-  SDOperand CopyValueToVirtualRegister(SelectionDAGLowering &SDL,
-                                       Value *V, unsigned Reg);
   void SelectBasicBlock(BasicBlock *BB, MachineFunction &MF,
                         FunctionLoweringInfo &FuncInfo);