class TargetLowering;
class TargetInstrInfo;
class FunctionLoweringInfo;
- class HazardRecognizer;
+ class ScheduleHazardRecognizer;
class GCFunctionInfo;
- class ScheduleDAG;
+ class ScheduleDAGSDNodes;
/// SelectionDAGISel - This is the common base class used for SelectionDAG-based
/// pattern-matching instruction selectors.
class SelectionDAGISel : public FunctionPass {
public:
+ const TargetMachine &TM;
TargetLowering &TLI;
- MachineRegisterInfo *RegInfo;
FunctionLoweringInfo *FuncInfo;
+ MachineFunction *MF;
+ MachineRegisterInfo *RegInfo;
SelectionDAG *CurDAG;
SelectionDAGLowering *SDL;
MachineBasicBlock *BB;
AliasAnalysis *AA;
GCFunctionInfo *GFI;
- bool Fast;
+ CodeGenOpt::Level OptLevel;
static char ID;
- explicit SelectionDAGISel(TargetLowering &tli, bool fast = false);
+ explicit SelectionDAGISel(TargetMachine &tm,
+ CodeGenOpt::Level OL = CodeGenOpt::Default);
virtual ~SelectionDAGISel();
TargetLowering &getTargetLowering() { return TLI; }
/// U can be folded during instruction selection that starts at Root and
/// folding N is profitable.
virtual
- bool IsLegalAndProfitableToFold(SDNode *N, SDNode *U, SDNode *Root) const {
- return true;
- }
-
+ bool IsLegalAndProfitableToFold(SDNode *N, SDNode *U, SDNode *Root) const;
+
/// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
/// to use for this target when scheduling the DAG.
- virtual HazardRecognizer *CreateTargetHazardRecognizer();
+ virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer();
protected:
/// DAGSize - Size of DAG being instruction selected.
bool HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB, FastISel *F);
- /// Pick a safe ordering for instructions for each target node in the
- /// graph.
- ScheduleDAG *Schedule();
+ /// Create the scheduler. If a specific scheduler was specified
+ /// via the SchedulerRegistry, use it, otherwise select the
+ /// one preferred by the target.
+ ///
+ ScheduleDAGSDNodes *CreateScheduler();
};
}