no really, I can spell!

[oota-llvm.git] / include / llvm / CodeGen / SelectionDAGISel.h

diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h
index 2f85e50a717f9ee56be561553aa56c790766d097..d2c0dc420f8a21261ab6fa0023666d842edad1c6 100644 (file)
--- a/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/include/llvm/CodeGen/SelectionDAGISel.h
@@ -21,35 +21,41 @@
 #include "llvm/CodeGen/SelectionDAG.h"
 
 namespace llvm {
+  class FastISel;
   class SelectionDAGLowering;
   class SDValue;
   class MachineRegisterInfo;
   class MachineBasicBlock;
   class MachineFunction;
   class MachineInstr;
+  class MachineModuleInfo;
+  class DwarfWriter;
   class TargetLowering;
+  class TargetInstrInfo;
   class FunctionLoweringInfo;
-  class HazardRecognizer;
+  class ScheduleHazardRecognizer;
   class GCFunctionInfo;
-  class ScheduleDAG;
+  class ScheduleDAGSDNodes;
  
 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
 /// pattern-matching instruction selectors.
 class SelectionDAGISel : public FunctionPass {
 public:
+  const TargetMachine &TM;
   TargetLowering &TLI;
-  MachineRegisterInfo *RegInfo;
   FunctionLoweringInfo *FuncInfo;
+  MachineFunction *MF;
+  MachineRegisterInfo *RegInfo;
   SelectionDAG *CurDAG;
   SelectionDAGLowering *SDL;
   MachineBasicBlock *BB;
   AliasAnalysis *AA;
   GCFunctionInfo *GFI;
-  bool Fast;
-  std::vector<SDNode*> TopOrder;
+  CodeGenOpt::Level OptLevel;
   static char ID;
 
-  explicit SelectionDAGISel(TargetLowering &tli, bool fast = false);
+  explicit SelectionDAGISel(TargetMachine &tm,
+                            CodeGenOpt::Level OL = CodeGenOpt::Default);
   virtual ~SelectionDAGISel();
   
   TargetLowering &getTargetLowering() { return TLI; }
@@ -62,10 +68,9 @@ public:
 
   virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
   virtual void InstructionSelect() = 0;
-  virtual void InstructionSelectPostProcessing() {}
   
   void SelectRootInit() {
-    DAGSize = CurDAG->AssignTopologicalOrder(TopOrder);
+    DAGSize = CurDAG->AssignTopologicalOrder();
   }
 
   /// SelectInlineAsmMemoryOperand - Select the specified address as a target
@@ -79,15 +84,15 @@ public:
     return true;
   }
 
-  /// CanBeFoldedBy - Returns true if the specific operand node N of U can be
-  /// folded during instruction selection that starts at Root?
-  virtual bool CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) const {
-    return true;
-  }
-  
+  /// IsLegalAndProfitableToFold - Returns true if the specific operand node N of
+  /// U can be folded during instruction selection that starts at Root and
+  /// folding N is profitable.
+  virtual
+  bool IsLegalAndProfitableToFold(SDNode *N, SDNode *U, SDNode *Root) const;
+
   /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
   /// to use for this target when scheduling the DAG.
-  virtual HazardRecognizer *CreateTargetHazardRecognizer();
+  virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer();
   
 protected:
   /// DAGSize - Size of DAG being instruction selected.
@@ -105,7 +110,10 @@ protected:
                     int64_t DesiredMaskS) const;
   
 private:
-  void SelectAllBasicBlocks(Function &Fn, MachineFunction &MF);
+  void SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
+                            MachineModuleInfo *MMI,
+                            DwarfWriter *DW,
+                            const TargetInstrInfo &TII);
   void FinishBasicBlock();
 
   void SelectBasicBlock(BasicBlock *LLVMBB,
@@ -118,9 +126,13 @@ private:
 
   void HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB);
 
-  /// Pick a safe ordering for instructions for each target node in the
-  /// graph.
-  ScheduleDAG *Schedule();
+  bool HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB, FastISel *F);
+
+  /// Create the scheduler. If a specific scheduler was specified
+  /// via the SchedulerRegistry, use it, otherwise select the
+  /// one preferred by the target.
+  ///
+  ScheduleDAGSDNodes *CreateScheduler();
 };
 
 }