no really, I can spell!

[oota-llvm.git] / include / llvm / CodeGen / SelectionDAGISel.h

diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h
index 5d244862048555619fca6f0e38bc6f08dfe1a6d5..d2c0dc420f8a21261ab6fa0023666d842edad1c6 100644 (file)
--- a/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/include/llvm/CodeGen/SelectionDAGISel.h
@@ -29,29 +29,33 @@ namespace llvm {
   class MachineFunction;
   class MachineInstr;
   class MachineModuleInfo;
+  class DwarfWriter;
   class TargetLowering;
   class TargetInstrInfo;
   class FunctionLoweringInfo;
-  class HazardRecognizer;
+  class ScheduleHazardRecognizer;
   class GCFunctionInfo;
-  class ScheduleDAG;
+  class ScheduleDAGSDNodes;
  
 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
 /// pattern-matching instruction selectors.
 class SelectionDAGISel : public FunctionPass {
 public:
+  const TargetMachine &TM;
   TargetLowering &TLI;
-  MachineRegisterInfo *RegInfo;
   FunctionLoweringInfo *FuncInfo;
+  MachineFunction *MF;
+  MachineRegisterInfo *RegInfo;
   SelectionDAG *CurDAG;
   SelectionDAGLowering *SDL;
   MachineBasicBlock *BB;
   AliasAnalysis *AA;
   GCFunctionInfo *GFI;
-  bool Fast;
+  CodeGenOpt::Level OptLevel;
   static char ID;
 
-  explicit SelectionDAGISel(TargetLowering &tli, bool fast = false);
+  explicit SelectionDAGISel(TargetMachine &tm,
+                            CodeGenOpt::Level OL = CodeGenOpt::Default);
   virtual ~SelectionDAGISel();
   
   TargetLowering &getTargetLowering() { return TLI; }
@@ -84,13 +88,11 @@ public:
   /// U can be folded during instruction selection that starts at Root and
   /// folding N is profitable.
   virtual
-  bool IsLegalAndProfitableToFold(SDNode *N, SDNode *U, SDNode *Root) const {
-    return true;
-  }
-  
+  bool IsLegalAndProfitableToFold(SDNode *N, SDNode *U, SDNode *Root) const;
+
   /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
   /// to use for this target when scheduling the DAG.
-  virtual HazardRecognizer *CreateTargetHazardRecognizer();
+  virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer();
   
 protected:
   /// DAGSize - Size of DAG being instruction selected.
@@ -110,6 +112,7 @@ protected:
 private:
   void SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
                             MachineModuleInfo *MMI,
+                            DwarfWriter *DW,
                             const TargetInstrInfo &TII);
   void FinishBasicBlock();
 
@@ -125,9 +128,11 @@ private:
 
   bool HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB, FastISel *F);
 
-  /// Pick a safe ordering for instructions for each target node in the
-  /// graph.
-  ScheduleDAG *Schedule();
+  /// Create the scheduler. If a specific scheduler was specified
+  /// via the SchedulerRegistry, use it, otherwise select the
+  /// one preferred by the target.
+  ///
+  ScheduleDAGSDNodes *CreateScheduler();
 };
 
 }