improve comments.

[oota-llvm.git] / include / llvm / CodeGen / SelectionDAGNodes.h

diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h
index adf04782d091c3ebaa7e4da3eca2f97c38a91dab..62c3769ebe6124438576d010d78936f2b1c0958a 100644 (file)
--- a/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -303,7 +303,9 @@ namespace ISD {
     INSERT_VECTOR_ELT,
 
     /// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR
-    /// identified by the (potentially variable) element number IDX.
+    /// identified by the (potentially variable) element number IDX.  If the
+    /// return type is an integer type larger than the element type of the
+    /// vector, the result is extended to the width of the return type.
     EXTRACT_VECTOR_ELT,
 
     /// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of
@@ -363,12 +365,11 @@ namespace ISD {
     // them with (op #2) as a CondCodeSDNode.
     SETCC,
 
-    // Vector SetCC operator - This evaluates to a vector of integer elements
-    // with the high bit in each element set to true if the comparison is true
-    // and false if the comparison is false.  All other bits in each element
-    // are undefined.  The operands to this are the left and right operands
-    // to compare (ops #0, and #1) and the condition code to compare them with
-    // (op #2) as a CondCodeSDNode.
+    // RESULT = VSETCC(LHS, RHS, COND) operator - This evaluates to a vector of
+    // integer elements with all bits of the result elements set to true if the
+    // comparison is true or all cleared if the comparison is false.  The
+    // operands to this are the left and right operands to compare (LHS/RHS) and
+    // the condition code to compare them with (COND) as a CondCodeSDNode.
     VSETCC,
 
     // SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded
@@ -2257,6 +2258,7 @@ class CallSDNode : public SDNode {
   unsigned CallingConv;
   bool IsVarArg;
   bool IsTailCall;
+  unsigned NumFixedArgs;
   // We might eventually want a full-blown Attributes for the result; that
   // will expand the size of the representation.  At the moment we only
   // need Inreg.
@@ -2264,10 +2266,10 @@ class CallSDNode : public SDNode {
   friend class SelectionDAG;
   CallSDNode(unsigned cc, DebugLoc dl, bool isvararg, bool istailcall,
              bool isinreg, SDVTList VTs, const SDValue *Operands,
-             unsigned numOperands)
+             unsigned numOperands, unsigned numFixedArgs)
     : SDNode(ISD::CALL, dl, VTs, Operands, numOperands),
       CallingConv(cc), IsVarArg(isvararg), IsTailCall(istailcall),
-      Inreg(isinreg) {}
+      NumFixedArgs(numFixedArgs), Inreg(isinreg) {}
 public:
   unsigned getCallingConv() const { return CallingConv; }
   unsigned isVarArg() const { return IsVarArg; }
@@ -2284,6 +2286,12 @@ public:
   SDValue getCallee() const { return getOperand(1); }
 
   unsigned getNumArgs() const { return (getNumOperands() - 2) / 2; }
+  unsigned getNumFixedArgs() const {
+    if (isVarArg())
+      return NumFixedArgs;
+    else
+      return getNumArgs();
+  }
   SDValue getArg(unsigned i) const { return getOperand(2+2*i); }
   SDValue getArgFlagsVal(unsigned i) const {
     return getOperand(3+2*i);