namespace ISD {
//===--------------------------------------------------------------------===//
- /// ISD::NodeType enum - This enum defines all of the operators valid in a
- /// SelectionDAG.
+ /// ISD::NodeType enum - This enum defines the target-independent operators
+ /// for a SelectionDAG.
///
- /// These are sometimes called the target-independent operators; targets
- /// may also define target-dependent operators. For example, on x86, these
- /// are the enum values in the X86ISD namespace. Targets should aim to use
- /// target-independent operators to model their instruction sets as much
- /// as possible, and only use target-dependent operators when they have
- /// special requirements.
+ /// Targets may also define target-dependent operator codes for SDNodes. For
+ /// example, on x86, these are the enum values in the X86ISD namespace.
+ /// Targets should aim to use target-independent operators to model their
+ /// instruction sets as much as possible, and only use target-dependent
+ /// operators when they have special requirements.
+ ///
+ /// Finally, during and after selection proper, SNodes may use special
+ /// operator codes that correspond directly with MachineInstr opcodes. These
+ /// are used to represent selected instructions. See the isMachineOpcode()
+ /// and getMachineOpcode() member functions of SDNode.
///
enum NodeType {
// DELETED_NODE - This is an illegal flag value that is used to catch
: SDNode(Opc, VTs) {
InitOperands(&Op, X);
}
+ UnarySDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, SDValue X)
+ : SDNode(Opc, dl, VTs) {
+ InitOperands(&Op, X);
+ }
};
/// BinarySDNode - This class is used for two-operand SDNodes. This is solely
: SDNode(Opc, VTs) {
InitOperands(Ops, X, Y);
}
+ BinarySDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, SDValue X, SDValue Y)
+ : SDNode(Opc, dl, VTs) {
+ InitOperands(Ops, X, Y);
+ }
};
/// TernarySDNode - This class is used for three-operand SDNodes. This is solely
: SDNode(Opc, VTs) {
InitOperands(Ops, X, Y, Z);
}
+ TernarySDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, SDValue X, SDValue Y,
+ SDValue Z)
+ : SDNode(Opc, dl, VTs) {
+ InitOperands(Ops, X, Y, Z);
+ }
};
MVT MemoryVT, const Value *srcValue, int SVOff,
unsigned alignment, bool isvolatile);
+ MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT MemoryVT,
+ const Value *srcValue, int SVOff,
+ unsigned alignment, bool isvolatile);
+
+ MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, const SDValue *Ops,
+ unsigned NumOps, MVT MemoryVT, const Value *srcValue, int SVOff,
+ unsigned alignment, bool isvolatile);
+
/// Returns alignment and volatility of the memory access
unsigned getAlignment() const { return (1u << (Flags >> 1)) >> 1; }
bool isVolatile() const { return Flags & 1; }
Align, /*isVolatile=*/true) {
InitOperands(Ops, Chain, Ptr, Val);
}
+ AtomicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTL, MVT MemVT,
+ SDValue Chain, SDValue Ptr,
+ SDValue Cmp, SDValue Swp, const Value* SrcVal,
+ unsigned Align=0)
+ : MemSDNode(Opc, dl, VTL, MemVT, SrcVal, /*SVOffset=*/0,
+ Align, /*isVolatile=*/true) {
+ InitOperands(Ops, Chain, Ptr, Cmp, Swp);
+ }
+ AtomicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTL, MVT MemVT,
+ SDValue Chain, SDValue Ptr,
+ SDValue Val, const Value* SrcVal, unsigned Align=0)
+ : MemSDNode(Opc, dl, VTL, MemVT, SrcVal, /*SVOffset=*/0,
+ Align, /*isVolatile=*/true) {
+ InitOperands(Ops, Chain, Ptr, Val);
+ }
const SDValue &getBasePtr() const { return getOperand(1); }
const SDValue &getVal() const { return getOperand(2); }
: MemSDNode(Opc, VTs, Ops, NumOps, MemoryVT, srcValue, SVO, Align, Vol),
ReadMem(ReadMem), WriteMem(WriteMem) {
}
+ MemIntrinsicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs,
+ const SDValue *Ops, unsigned NumOps,
+ MVT MemoryVT, const Value *srcValue, int SVO,
+ unsigned Align, bool Vol, bool ReadMem, bool WriteMem)
+ : MemSDNode(Opc, dl, VTs, Ops, NumOps, MemoryVT, srcValue, SVO, Align, Vol),
+ ReadMem(ReadMem), WriteMem(WriteMem) {
+ }
bool readMem() const { return ReadMem; }
bool writeMem() const { return WriteMem; }
explicit BasicBlockSDNode(MachineBasicBlock *mbb)
: SDNode(ISD::BasicBlock, getSDVTList(MVT::Other)), MBB(mbb) {
}
+ explicit BasicBlockSDNode(MachineBasicBlock *mbb, DebugLoc dl)
+ : SDNode(ISD::BasicBlock, dl, getSDVTList(MVT::Other)), MBB(mbb) {
+ }
public:
MachineBasicBlock *getBasicBlock() const { return MBB; }
: SDNode(NodeTy, getSDVTList(MVT::Other)), LabelID(id) {
InitOperands(&Chain, ch);
}
+ LabelSDNode(unsigned NodeTy, DebugLoc dl, SDValue ch, unsigned id)
+ : SDNode(NodeTy, dl, getSDVTList(MVT::Other)), LabelID(id) {
+ InitOperands(&Chain, ch);
+ }
public:
unsigned getLabelID() const { return LabelID; }
: SDNode(isTarget ? ISD::TargetExternalSymbol : ISD::ExternalSymbol,
getSDVTList(VT)), Symbol(Sym) {
}
+ ExternalSymbolSDNode(bool isTarget, DebugLoc dl, const char *Sym, MVT VT)
+ : SDNode(isTarget ? ISD::TargetExternalSymbol : ISD::ExternalSymbol, dl,
+ getSDVTList(VT)), Symbol(Sym) {
+ }
public:
const char *getSymbol() const { return Symbol; }
: SDNode(ISD::CALL, VTs, Operands, numOperands),
CallingConv(cc), IsVarArg(isvararg), IsTailCall(istailcall),
Inreg(isinreg) {}
+ CallSDNode(unsigned cc, DebugLoc dl, bool isvararg, bool istailcall,
+ bool isinreg, SDVTList VTs, const SDValue *Operands,
+ unsigned numOperands)
+ : SDNode(ISD::CALL, dl, VTs, Operands, numOperands),
+ CallingConv(cc), IsVarArg(isvararg), IsTailCall(istailcall),
+ Inreg(isinreg) {}
public:
unsigned getCallingConv() const { return CallingConv; }
unsigned isVarArg() const { return IsVarArg; }
assert((getOffset().getOpcode() == ISD::UNDEF || isIndexed()) &&
"Only indexed loads and stores have a non-undef offset operand");
}
+ LSBaseSDNode(ISD::NodeType NodeTy, DebugLoc dl, SDValue *Operands,
+ unsigned numOperands, SDVTList VTs, ISD::MemIndexedMode AM,
+ MVT VT, const Value *SV, int SVO, unsigned Align, bool Vol)
+ : MemSDNode(NodeTy, dl, VTs, VT, SV, SVO, Align, Vol) {
+ SubclassData = AM;
+ InitOperands(Ops, Operands, numOperands);
+ assert(Align != 0 && "Loads and stores should have non-zero aligment");
+ assert((getOffset().getOpcode() == ISD::UNDEF || isIndexed()) &&
+ "Only indexed loads and stores have a non-undef offset operand");
+ }
const SDValue &getOffset() const {
return getOperand(getOpcode() == ISD::LOAD ? 2 : 3);
VTs, AM, LVT, SV, O, Align, Vol) {
SubclassData |= (unsigned short)ETy << 3;
}
+ LoadSDNode(SDValue *ChainPtrOff, DebugLoc dl, SDVTList VTs,
+ ISD::MemIndexedMode AM, ISD::LoadExtType ETy, MVT LVT,
+ const Value *SV, int O=0, unsigned Align=0, bool Vol=false)
+ : LSBaseSDNode(ISD::LOAD, dl, ChainPtrOff, 3,
+ VTs, AM, LVT, SV, O, Align, Vol) {
+ SubclassData |= (unsigned short)ETy << 3;
+ }
public:
/// getExtensionType - Return whether this is a plain node,
VTs, AM, SVT, SV, O, Align, Vol) {
SubclassData |= (unsigned short)isTrunc << 3;
}
+ StoreSDNode(SDValue *ChainValuePtrOff, DebugLoc dl, SDVTList VTs,
+ ISD::MemIndexedMode AM, bool isTrunc, MVT SVT,
+ const Value *SV, int O=0, unsigned Align=0, bool Vol=false)
+ : LSBaseSDNode(ISD::STORE, dl, ChainValuePtrOff, 4,
+ VTs, AM, SVT, SV, O, Align, Vol) {
+ SubclassData |= (unsigned short)isTrunc << 3;
+ }
public:
/// isTruncatingStore - Return true if the op does a truncation before store.
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