Use MDNode * directly as an RecordSourceLine() argument.

[oota-llvm.git] / include / llvm / IntrinsicsARM.td

diff --git a/include/llvm/IntrinsicsARM.td b/include/llvm/IntrinsicsARM.td
index 7b7208276383bff1b5e88ff39b66eafd18537445..c408a2f374ec451db24ef6b669e19e04ee46a394 100644 (file)
--- a/include/llvm/IntrinsicsARM.td
+++ b/include/llvm/IntrinsicsARM.td
@@ -61,9 +61,6 @@ let TargetPrefix = "arm" in {  // All intrinsics start with "llvm.arm.".
                  LLVMTruncatedElementVectorType<0>,
                  LLVMTruncatedElementVectorType<0>],
                 [IntrNoMem]>;
-  class Neon_2Result_Intrinsic
-    : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
-                [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
   class Neon_CvtFxToFP_Intrinsic
     : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
   class Neon_CvtFPToFx_Intrinsic
@@ -300,26 +297,21 @@ def int_arm_neon_vmovls : Neon_1Arg_Long_Intrinsic;
 def int_arm_neon_vmovlu : Neon_1Arg_Long_Intrinsic;
 
 // Vector Table Lookup.
+// The first 1-4 arguments are the table.
 def int_arm_neon_vtbl1 : Neon_Tbl2Arg_Intrinsic;
 def int_arm_neon_vtbl2 : Neon_Tbl3Arg_Intrinsic;
 def int_arm_neon_vtbl3 : Neon_Tbl4Arg_Intrinsic;
 def int_arm_neon_vtbl4 : Neon_Tbl5Arg_Intrinsic;
 
 // Vector Table Extension.
+// Some elements of the destination vector may not be updated, so the original
+// value of that vector is passed as the first argument.  The next 1-4
+// arguments after that are the table.
 def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic;
 def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
 def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
 def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
 
-// Vector Transpose.
-def int_arm_neon_vtrn : Neon_2Result_Intrinsic;
-
-// Vector Interleave (vzip).
-def int_arm_neon_vzip : Neon_2Result_Intrinsic;
-
-// Vector Deinterleave (vuzp).
-def int_arm_neon_vuzp : Neon_2Result_Intrinsic;
-
 let TargetPrefix = "arm" in {
 
   // De-interleaving vector loads from N-element structures.
@@ -334,6 +326,23 @@ let TargetPrefix = "arm" in {
                                      LLVMMatchType<0>, LLVMMatchType<0>],
                                     [llvm_ptr_ty], [IntrReadArgMem]>;
 
+  // Vector load N-element structure to one lane.
+  def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
+                                        [llvm_ptr_ty, LLVMMatchType<0>,
+                                         LLVMMatchType<0>, llvm_i32_ty],
+                                        [IntrReadArgMem]>;
+  def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
+                                         LLVMMatchType<0>],
+                                        [llvm_ptr_ty, LLVMMatchType<0>,
+                                         LLVMMatchType<0>, LLVMMatchType<0>,
+                                         llvm_i32_ty], [IntrReadArgMem]>;
+  def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
+                                         LLVMMatchType<0>, LLVMMatchType<0>],
+                                        [llvm_ptr_ty, LLVMMatchType<0>,
+                                         LLVMMatchType<0>, LLVMMatchType<0>,
+                                         LLVMMatchType<0>, llvm_i32_ty],
+                                        [IntrReadArgMem]>;
+
   // Interleaving vector stores from N-element structures.
   def int_arm_neon_vst1 : Intrinsic<[llvm_void_ty],
                                     [llvm_ptr_ty, llvm_anyvector_ty],
@@ -349,4 +358,19 @@ let TargetPrefix = "arm" in {
                                     [llvm_ptr_ty, llvm_anyvector_ty,
                                      LLVMMatchType<0>, LLVMMatchType<0>,
                                      LLVMMatchType<0>], [IntrWriteArgMem]>;
+
+  // Vector store N-element structure from one lane.
+  def int_arm_neon_vst2lane : Intrinsic<[llvm_void_ty],
+                                        [llvm_ptr_ty, llvm_anyvector_ty,
+                                         LLVMMatchType<0>, llvm_i32_ty],
+                                        [IntrWriteArgMem]>;
+  def int_arm_neon_vst3lane : Intrinsic<[llvm_void_ty],
+                                        [llvm_ptr_ty, llvm_anyvector_ty,
+                                         LLVMMatchType<0>, LLVMMatchType<0>,
+                                         llvm_i32_ty], [IntrWriteArgMem]>;
+  def int_arm_neon_vst4lane : Intrinsic<[llvm_void_ty],
+                                        [llvm_ptr_ty, llvm_anyvector_ty,
+                                         LLVMMatchType<0>, LLVMMatchType<0>,
+                                         LLVMMatchType<0>, llvm_i32_ty],
+                                        [IntrWriteArgMem]>;
 }