#ifndef LLVM_MC_MCINSTRITINERARIES_H
#define LLVM_MC_MCINSTRITINERARIES_H
+#include "llvm/MC/MCSchedule.h"
#include <algorithm>
namespace llvm {
//===----------------------------------------------------------------------===//
-/// Instruction stage - These values represent a non-pipelined step in
+/// These values represent a non-pipelined step in
/// the execution of an instruction. Cycles represents the number of
/// discrete time slots needed to complete the stage. Units represent
/// the choice of functional units that can be used to complete the
int NextCycles_; ///< Number of machine cycles to next stage
ReservationKinds Kind_; ///< Kind of the FU reservation
- /// getCycles - returns the number of cycles the stage is occupied
+ /// \brief Returns the number of cycles the stage is occupied.
unsigned getCycles() const {
return Cycles_;
}
- /// getUnits - returns the choice of FUs
+ /// \brief Returns the choice of FUs.
unsigned getUnits() const {
return Units_;
}
return Kind_;
}
- /// getNextCycles - returns the number of cycles from the start of
- /// this stage to the start of the next stage in the itinerary
+ /// \brief Returns the number of cycles from the start of this stage to the
+ /// start of the next stage in the itinerary
unsigned getNextCycles() const {
return (NextCycles_ >= 0) ? (unsigned)NextCycles_ : Cycles_;
}
//===----------------------------------------------------------------------===//
-/// Instruction itinerary - An itinerary represents the scheduling
-/// information for an instruction. This includes a set of stages
-/// occupies by the instruction, and the pipeline cycle in which
-/// operands are read and written.
+/// An itinerary represents the scheduling information for an instruction.
+/// This includes a set of stages occupied by the instruction and the pipeline
+/// cycle in which operands are read and written.
///
struct InstrItinerary {
- unsigned NumMicroOps; ///< # of micro-ops, 0 means it's variable
+ int NumMicroOps; ///< # of micro-ops, -1 means it's variable
unsigned FirstStage; ///< Index of first stage in itinerary
unsigned LastStage; ///< Index of last + 1 stage in itinerary
unsigned FirstOperandCycle; ///< Index of first operand rd/wr
//===----------------------------------------------------------------------===//
-/// Instruction itinerary properties - These properties provide general
-/// information about the microarchitecture to the scheduler.
-///
-struct InstrItineraryProps {
- // IssueWidth is the maximum number of instructions that may be scheduled in
- // the same per-cycle group.
- unsigned IssueWidth;
- static const unsigned DefaultIssueWidth = 1;
-
- // MinLatency is the minimum latency between a register write
- // followed by a data dependent read. This determines which
- // instructions may be scheduled in the same per-cycle group. This
- // is distinct from *expected* latency, which determines the likely
- // critical path but does not guarantee a pipeline
- // hazard. MinLatency can always be overridden by the number of
- // InstrStage cycles.
- //
- // (-1) Standard in-order processor.
- // Use InstrItinerary OperandCycles as MinLatency.
- // If no OperandCycles exist, then use the cycle of the last InstrStage.
- //
- // (0) Out-of-order processor, or in-order with bundled dependencies.
- // RAW dependencies may be dispatched in the same cycle.
- // Optional InstrItinerary OperandCycles provides expected latency.
- //
- // (>0) In-order processor with variable latencies.
- // Use the greater of this value or the cycle of the last InstrStage.
- // Optional InstrItinerary OperandCycles provides expected latency.
- // TODO: can't yet specify both min and expected latency per operand.
- int MinLatency;
- static const unsigned DefaultMinLatency = -1;
-
- // LoadLatency is the expected latency of load instructions.
- //
- // If MinLatency >= 0, this may be overriden for individual load opcodes by
- // InstrItinerary OperandCycles.
- unsigned LoadLatency;
- static const unsigned DefaultLoadLatency = 4;
-
- // HighLatency is the expected latency of "very high latency" operations.
- // See TargetInstrInfo::isHighLatencyDef().
- // By default, this is set to an arbitrarily high number of cycles
- // likely to have some impact on scheduling heuristics.
- // If MinLatency >= 0, this may be overriden by InstrItinData OperandCycles.
- unsigned HighLatency;
- static const unsigned DefaultHighLatency = 10;
-
- // Default's must be specified as static const literals so that tablegenerated
- // target code can use it in static initializers. The defaults need to be
- // initialized in this default ctor because some clients directly instantiate
- // InstrItineraryData instead of using a generated itinerary.
- InstrItineraryProps(): IssueWidth(DefaultMinLatency),
- MinLatency(DefaultMinLatency),
- LoadLatency(DefaultLoadLatency),
- HighLatency(DefaultHighLatency) {}
-
- InstrItineraryProps(unsigned iw, int ml, unsigned ll, unsigned hl):
- IssueWidth(iw), MinLatency(ml), LoadLatency(ll), HighLatency(hl) {}
-};
-
-//===----------------------------------------------------------------------===//
-/// Encapsulate all subtarget specific information for scheduling for use with
-/// SubtargetInfoKV.
-struct InstrItinerarySubtargetValue {
- const InstrItineraryProps *Props;
- const InstrItinerary *Itineraries;
-};
-
-//===----------------------------------------------------------------------===//
-/// Instruction itinerary Data - Itinerary data supplied by a subtarget to be
-/// used by a target.
+/// Itinerary data supplied by a subtarget to be used by a target.
///
class InstrItineraryData {
public:
- InstrItineraryProps Props;
+ MCSchedModel SchedModel; ///< Basic machine properties.
const InstrStage *Stages; ///< Array of stages selected
const unsigned *OperandCycles; ///< Array of operand cycles selected
const unsigned *Forwardings; ///< Array of pipeline forwarding pathes
const InstrItinerary *Itineraries; ///< Array of itineraries selected
/// Ctors.
- ///
- InstrItineraryData() : Stages(0), OperandCycles(0), Forwardings(0),
- Itineraries(0) {}
-
- InstrItineraryData(const InstrItineraryProps *P, const InstrStage *S,
- const unsigned *OS, const unsigned *F,
- const InstrItinerary *I)
- : Props(*P), Stages(S), OperandCycles(OS), Forwardings(F), Itineraries(I) {}
-
- /// isEmpty - Returns true if there are no itineraries.
- ///
- bool isEmpty() const { return Itineraries == 0; }
-
- /// isEndMarker - Returns true if the index is for the end marker
- /// itinerary.
- ///
+ InstrItineraryData() : SchedModel(MCSchedModel::GetDefaultSchedModel()),
+ Stages(nullptr), OperandCycles(nullptr),
+ Forwardings(nullptr), Itineraries(nullptr) {}
+
+ InstrItineraryData(const MCSchedModel &SM, const InstrStage *S,
+ const unsigned *OS, const unsigned *F)
+ : SchedModel(SM), Stages(S), OperandCycles(OS), Forwardings(F),
+ Itineraries(SchedModel.InstrItineraries) {}
+
+ /// \brief Returns true if there are no itineraries.
+ bool isEmpty() const { return Itineraries == nullptr; }
+
+ /// \brief Returns true if the index is for the end marker itinerary.
bool isEndMarker(unsigned ItinClassIndx) const {
return ((Itineraries[ItinClassIndx].FirstStage == ~0U) &&
(Itineraries[ItinClassIndx].LastStage == ~0U));
}
- /// beginStage - Return the first stage of the itinerary.
- ///
+ /// \brief Return the first stage of the itinerary.
const InstrStage *beginStage(unsigned ItinClassIndx) const {
unsigned StageIdx = Itineraries[ItinClassIndx].FirstStage;
return Stages + StageIdx;
}
- /// endStage - Return the last+1 stage of the itinerary.
- ///
+ /// \brief Return the last+1 stage of the itinerary.
const InstrStage *endStage(unsigned ItinClassIndx) const {
unsigned StageIdx = Itineraries[ItinClassIndx].LastStage;
return Stages + StageIdx;
}
- /// getStageLatency - Return the total stage latency of the given
- /// class. The latency is the maximum completion time for any stage
- /// in the itinerary.
- ///
- /// InstrStages override the itinerary's MinLatency property. In fact, if the
- /// stage latencies, which may be zero, are less than MinLatency,
- /// getStageLatency returns a value less than MinLatency.
- ///
- /// If no stages exist, MinLatency is used. If MinLatency is invalid (<0),
- /// then it defaults to one cycle.
+ /// \brief Return the total stage latency of the given class. The latency is
+ /// the maximum completion time for any stage in the itinerary. If no stages
+ /// exist, it defaults to one cycle.
unsigned getStageLatency(unsigned ItinClassIndx) const {
// If the target doesn't provide itinerary information, use a simple
- // non-zero default value for all instructions. Some target's provide a
- // dummy (Generic) itinerary which should be handled as if it's itinerary is
- // empty. We identify this by looking for a reference to stage zero (invalid
- // stage). This is different from beginStage == endStage != 0, which could
- // be used for zero-latency pseudo ops.
- if (isEmpty() || Itineraries[ItinClassIndx].FirstStage == 0)
- return (Props.MinLatency < 0) ? 1 : Props.MinLatency;
+ // non-zero default value for all instructions.
+ if (isEmpty())
+ return 1;
// Calculate the maximum completion time for any stage.
unsigned Latency = 0, StartCycle = 0;
Latency = std::max(Latency, StartCycle + IS->getCycles());
StartCycle += IS->getNextCycles();
}
-
return Latency;
}
- /// getOperandCycle - Return the cycle for the given class and
- /// operand. Return -1 if no cycle is specified for the operand.
- ///
+ /// \brief Return the cycle for the given class and operand. Return -1 if no
+ /// cycle is specified for the operand.
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const {
if (isEmpty())
return -1;
return (int)OperandCycles[FirstIdx + OperandIdx];
}
- /// hasPipelineForwarding - Return true if there is a pipeline forwarding
- /// between instructions of itinerary classes DefClass and UseClasses so that
- /// value produced by an instruction of itinerary class DefClass, operand
- /// index DefIdx can be bypassed when it's read by an instruction of
- /// itinerary class UseClass, operand index UseIdx.
+ /// \brief Return true if there is a pipeline forwarding between instructions
+ /// of itinerary classes DefClass and UseClasses so that value produced by an
+ /// instruction of itinerary class DefClass, operand index DefIdx can be
+ /// bypassed when it's read by an instruction of itinerary class UseClass,
+ /// operand index UseIdx.
bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx,
unsigned UseClass, unsigned UseIdx) const {
unsigned FirstDefIdx = Itineraries[DefClass].FirstOperandCycle;
Forwardings[FirstUseIdx + UseIdx];
}
- /// getOperandLatency - Compute and return the use operand latency of a given
- /// itinerary class and operand index if the value is produced by an
- /// instruction of the specified itinerary class and def operand index.
+ /// \brief Compute and return the use operand latency of a given itinerary
+ /// class and operand index if the value is produced by an instruction of the
+ /// specified itinerary class and def operand index.
int getOperandLatency(unsigned DefClass, unsigned DefIdx,
unsigned UseClass, unsigned UseIdx) const {
if (isEmpty())
return UseCycle;
}
- /// isMicroCoded - Return true if the instructions in the given class decode
- /// to more than one micro-ops.
- bool isMicroCoded(unsigned ItinClassIndx) const {
+ /// \brief Return the number of micro-ops that the given class decodes to.
+ /// Return -1 for classes that require dynamic lookup via TargetInstrInfo.
+ int getNumMicroOps(unsigned ItinClassIndx) const {
if (isEmpty())
- return false;
- return Itineraries[ItinClassIndx].NumMicroOps != 1;
+ return 1;
+ return Itineraries[ItinClassIndx].NumMicroOps;
}
};
-
} // End llvm namespace
#endif
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