namespace llvm {
+/// An unsigned integer type large enough to represent all physical registers,
+/// but not necessarily virtual registers.
+typedef uint16_t MCPhysReg;
+
/// MCRegisterClass - Base class of TargetRegisterClass.
class MCRegisterClass {
public:
- typedef const uint16_t* iterator;
- typedef const uint16_t* const_iterator;
+ typedef const MCPhysReg* iterator;
+ typedef const MCPhysReg* const_iterator;
const char *Name;
const iterator RegsBegin;
unsigned NumClasses; // Number of entries in the array
unsigned NumRegUnits; // Number of regunits.
const uint16_t (*RegUnitRoots)[2]; // Pointer to regunit root table.
- const uint16_t *DiffLists; // Pointer to the difflists array
+ const MCPhysReg *DiffLists; // Pointer to the difflists array
const char *RegStrings; // Pointer to the string table.
const uint16_t *SubRegIndices; // Pointer to the subreg lookup
// array.
/// defined below.
class DiffListIterator {
uint16_t Val;
- const uint16_t *List;
+ const MCPhysReg *List;
protected:
/// Create an invalid iterator. Call init() to point to something useful.
/// init - Point the iterator to InitVal, decoding subsequent values from
/// DiffList. The iterator will initially point to InitVal, sub-classes are
/// responsible for skipping the seed value if it is not part of the list.
- void init(uint16_t InitVal, const uint16_t *DiffList) {
+ void init(MCPhysReg InitVal, const MCPhysReg *DiffList) {
Val = InitVal;
List = DiffList;
}
/// is the caller's responsibility (by checking for a 0 return value).
unsigned advance() {
assert(isValid() && "Cannot move off the end of the list.");
- uint16_t D = *List++;
+ MCPhysReg D = *List++;
Val += D;
return D;
}
const MCRegisterClass *C, unsigned NC,
const uint16_t (*RURoots)[2],
unsigned NRU,
- const uint16_t *DL,
+ const MCPhysReg *DL,
const char *Strings,
const uint16_t *SubIndices,
unsigned NumIndices,
return NumRegs;
}
+ /// getNumSubRegIndices - Return the number of sub-register indices
+ /// understood by the target. Index 0 is reserved for the no-op sub-register,
+ /// while 1 to getNumSubRegIndices() - 1 represent real sub-registers.
+ unsigned getNumSubRegIndices() const {
+ return NumSubRegIndices;
+ }
+
/// getNumRegUnits - Return the number of (native) register units in the
/// target. Register units are numbered from 0 to getNumRegUnits() - 1. They
/// can be accessed through MCRegUnitIterator defined below.
/// number. Returns -1 if there is no equivalent value. The second
/// parameter allows targets to use different numberings for EH info and
/// debugging info.
- int getDwarfRegNum(unsigned RegNum, bool isEH) const {
- const DwarfLLVMRegPair *M = isEH ? EHL2DwarfRegs : L2DwarfRegs;
- unsigned Size = isEH ? EHL2DwarfRegsSize : L2DwarfRegsSize;
-
- DwarfLLVMRegPair Key = { RegNum, 0 };
- const DwarfLLVMRegPair *I = std::lower_bound(M, M+Size, Key);
- if (I == M+Size || I->FromReg != RegNum)
- return -1;
- return I->ToReg;
- }
+ int getDwarfRegNum(unsigned RegNum, bool isEH) const;
/// getLLVMRegNum - Map a dwarf register back to a target register.
///
- int getLLVMRegNum(unsigned RegNum, bool isEH) const {
- const DwarfLLVMRegPair *M = isEH ? EHDwarf2LRegs : Dwarf2LRegs;
- unsigned Size = isEH ? EHDwarf2LRegsSize : Dwarf2LRegsSize;
-
- DwarfLLVMRegPair Key = { RegNum, 0 };
- const DwarfLLVMRegPair *I = std::lower_bound(M, M+Size, Key);
- assert(I != M+Size && I->FromReg == RegNum && "Invalid RegNum");
- return I->ToReg;
- }
+ int getLLVMRegNum(unsigned RegNum, bool isEH) const;
/// getSEHRegNum - Map a target register to an equivalent SEH register
/// number. Returns LLVM register number if there is no equivalent value.
- int getSEHRegNum(unsigned RegNum) const {
- const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum);
- if (I == L2SEHRegs.end()) return (int)RegNum;
- return I->second;
- }
+ int getSEHRegNum(unsigned RegNum) const;
regclass_iterator regclass_begin() const { return Classes; }
regclass_iterator regclass_end() const { return Classes+NumClasses; }
/// getRegClass - Returns the register class associated with the enumeration
/// value. See class MCOperandInfo.
- const MCRegisterClass getRegClass(unsigned i) const {
+ const MCRegisterClass& getRegClass(unsigned i) const {
assert(i < getNumRegClasses() && "Register Class ID out of range");
return Classes[i];
}
}
};
-inline
-unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
- const MCRegisterClass *RC) const {
- for (MCSuperRegIterator Supers(Reg, this); Supers.isValid(); ++Supers)
- if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
- return *Supers;
- return 0;
-}
-
-inline
-unsigned MCRegisterInfo::getSubReg(unsigned Reg, unsigned Idx) const {
- // Get a pointer to the corresponding SubRegIndices list. This list has the
- // name of each sub-register in the same order as MCSubRegIterator.
- const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
- for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI)
- if (*SRI == Idx)
- return *Subs;
- return 0;
-}
-
-inline
-unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const {
- // Get a pointer to the corresponding SubRegIndices list. This list has the
- // name of each sub-register in the same order as MCSubRegIterator.
- const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
- for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI)
- if (*Subs == SubReg)
- return *SRI;
- return 0;
-}
-
//===----------------------------------------------------------------------===//
// Register Units
//===----------------------------------------------------------------------===//
projects / oota-llvm.git / blobdiff