-//===- Target/MRegisterInfo.h - Target Register Information -------*-C++-*-===//
+//===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
//
// This file describes an abstract interface used to get information about a
// target machines register file. This information is used for a variety of
#include "llvm/CodeGen/MachineBasicBlock.h"
#include <cassert>
+#include <functional>
+
+namespace llvm {
class Type;
class MachineFunction;
+class MachineInstr;
/// MRegisterDesc - This record contains all of the information known about a
/// particular register. The AliasSet field (if not null) contains a pointer to
/// Registers that this does not apply to simply should set this to null.
///
struct MRegisterDesc {
- const char *Name; // Assembly language name for the register
- const unsigned *AliasSet; // Register Alias Set, described above
- unsigned Flags; // Flags identifying register properties (below)
- unsigned TSFlags; // Target Specific Flags
-};
-
-/// MRF namespace - This namespace contains flags that pertain to machine
-/// registers
-///
-namespace MRF { // MRF = Machine Register Flags
- enum {
- Other = 0 << 0, // This is a non-standard register
- INT8 = 1 << 0, // This is an 8 bit integer register
- INT16 = 1 << 1, // This is a 16 bit integer register
- INT32 = 1 << 2, // This is a 32 bit integer register
- INT64 = 1 << 3, // This is a 64 bit integer register
- INT128 = 1 << 4, // This is a 128 bit integer register
-
- FP32 = 1 << 5, // This is a 32 bit floating point register
- FP64 = 1 << 6, // This is a 64 bit floating point register
- FP80 = 1 << 7, // This is a 80 bit floating point register
- FP128 = 1 << 8, // This is a 128 bit floating point register
- };
+ const char *Name; // Assembly language name for the register
+ const unsigned *AliasSet; // Register Alias Set, described above
+ unsigned char SpillSize; // Size of this register in bytes
+ unsigned char SpillAlignment; // Alignment of stack slot for this reg
};
class TargetRegisterClass {
return RegsBegin[i];
}
+ /// contains - Return true if the specified register is included in this
+ /// register class.
+ bool contains(unsigned Reg) const {
+ for (iterator I = begin(), E = end(); I != E; ++I)
+ if (*I == Reg) return true;
+ return false;
+ }
+
/// allocation_order_begin/end - These methods define a range of registers
/// which specify the registers in this class that are valid to register
/// allocate, and the preferred order to allocate them in. For example,
virtual ~MRegisterInfo();
public:
- enum { // Define some target independant constants
+ enum { // Define some target independent constants
/// NoRegister - This 'hard' register is a 'noop' register for all backends.
/// This is used as the destination register for instructions that do not
/// produce a value. Some frontends may use this as an operand register to
FirstVirtualRegister = 1024,
};
+ /// isPhysicalRegister - Return true if the specified register number is in
+ /// the physical register namespace.
+ static bool isPhysicalRegister(unsigned Reg) {
+ assert(Reg && "this is not a register!");
+ return Reg < FirstVirtualRegister;
+ }
+
+ /// isVirtualRegister - Return true if the specified register number is in
+ /// the virtual register namespace.
+ static bool isVirtualRegister(unsigned Reg) {
+ assert(Reg && "this is not a register!");
+ return Reg >= FirstVirtualRegister;
+ }
+
+ /// getAllocatableSet - Returns a bitset indexed by register number
+ /// indicating if a register is allocatable or not.
+ std::vector<bool> getAllocatableSet(MachineFunction &MF) const;
+
const MRegisterDesc &operator[](unsigned RegNo) const {
assert(RegNo < NumRegs &&
"Attempting to access record for invalid register number!");
return get(RegNo).Name;
}
+ /// getSpillSize - Return the size in bits required of a stack slot used to
+ /// spill register into.
+ unsigned getSpillSize(unsigned RegNo) const {
+ return get(RegNo).SpillSize;
+ }
+
+ /// getSpillAlignment - Return the alignment required by a stack slot used to
+ /// spill register into.
+ unsigned getSpillAlignment(unsigned RegNo) const {
+ return get(RegNo).SpillAlignment;
+ }
+
+ /// getNumRegs - Return the number of registers this target has
+ /// (useful for sizing arrays holding per register information)
+ unsigned getNumRegs() const {
+ return NumRegs;
+ }
+
+ /// areAliases - Returns true if the two registers alias each other,
+ /// false otherwise
+ bool areAliases(unsigned regA, unsigned regB) const {
+ for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
+ if (*Alias == regB) return true;
+ return false;
+ }
+
virtual const unsigned* getCalleeSaveRegs() const = 0;
//
/// Register class iterators
+ ///
regclass_iterator regclass_begin() const { return RegClassBegin; }
regclass_iterator regclass_end() const { return RegClassEnd; }
unsigned getNumRegClasses() const {
return regclass_end()-regclass_begin();
}
- virtual const TargetRegisterClass* getRegClassForType(const Type* Ty) const=0;
-
//===--------------------------------------------------------------------===//
- // Interfaces used by the register allocator and stack frame manipulation
- // passes to move data around between registers, immediates and memory.
+ // Interfaces used by the register allocator and stack frame
+ // manipulation passes to move data around between registers,
+ // immediates and memory. The return value is the number of
+ // instructions added to (negative if removed from) the basic block.
//
virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &MBBI,
- unsigned SrcReg, int FrameIndex,
- const TargetRegisterClass *RC) const = 0;
+ MachineBasicBlock::iterator MI,
+ unsigned SrcReg, int FrameIndex) const = 0;
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &MBBI,
- unsigned DestReg, int FrameIndex,
- const TargetRegisterClass *RC) const = 0;
+ MachineBasicBlock::iterator MI,
+ unsigned DestReg, int FrameIndex) const = 0;
virtual void copyRegToReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &MBBI,
- unsigned DestReg, unsigned SrcReg,
- const TargetRegisterClass *RC) const = 0;
-
+ MachineBasicBlock::iterator MI,
+ unsigned DestReg, unsigned SrcReg,
+ const TargetRegisterClass *RC) const = 0;
+
+
+ /// foldMemoryOperand - Attempt to fold a load or store of the
+ /// specified stack slot into the specified machine instruction for
+ /// the specified operand. If this is possible, a new instruction
+ /// is returned with the specified operand folded, otherwise NULL is
+ /// returned. The client is responsible for removing the old
+ /// instruction and adding the new one in the instruction stream
+ virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
+ unsigned OpNum,
+ int FrameIndex) const {
+ return 0;
+ }
/// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
/// frame setup/destroy instructions if they exist (-1 otherwise). Some
/// instructions. This method need only be implemented if using call frame
/// setup/destroy pseudo instructions.
///
- virtual void eliminateCallFramePseudoInstr(MachineFunction &MF,
- MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &I) const {
+ virtual void
+ eliminateCallFramePseudoInstr(MachineFunction &MF,
+ MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI) const {
assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
"eliminateCallFramePseudoInstr must be implemented if using"
" call frame setup/destroy pseudo instructions!");
/// processFunctionBeforeFrameFinalized - This method is called immediately
/// before the specified functions frame layout (MF.getFrameInfo()) is
/// finalized. Once the frame is finalized, MO_FrameIndex operands are
- /// replaced with direct constants. This method is optional.
+ /// replaced with direct constants. This method is optional. The return value
+ /// is the number of instructions added to (negative if removed from) the
+ /// basic block
///
- virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
+ virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
+ }
/// eliminateFrameIndex - This method must be overriden to eliminate abstract
/// frame indices from instructions which may use them. The instruction
/// referenced by the iterator contains an MO_FrameIndex operand which must be
/// eliminated by this method. This method may modify or replace the
/// specified instruction, as long as it keeps the iterator pointing the the
- /// finished product.
+ /// finished product. The return value is the number of instructions
+ /// added to (negative if removed from) the basic block.
///
- virtual void eliminateFrameIndex(MachineFunction &MF,
- MachineBasicBlock::iterator &II) const = 0;
+ virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI) const = 0;
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
- /// the function.
+ /// the function. The return value is the number of instructions
+ /// added to (negative if removed from) the basic block (entry for prologue).
+ ///
virtual void emitPrologue(MachineFunction &MF) const = 0;
virtual void emitEpilogue(MachineFunction &MF,
- MachineBasicBlock &MBB) const = 0;
+ MachineBasicBlock &MBB) const = 0;
};
+// This is useful when building DenseMaps keyed on virtual registers
+struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
+ unsigned operator()(unsigned Reg) const {
+ return Reg - MRegisterInfo::FirstVirtualRegister;
+ }
+};
+
+} // End llvm namespace
+
#endif
projects / oota-llvm.git / blobdiff