#ifndef LLVM_TARGET_MREGISTERINFO_H
#define LLVM_TARGET_MREGISTERINFO_H
-#include <cassert>
#include "llvm/CodeGen/MachineBasicBlock.h"
+#include <cassert>
+#include <functional>
namespace llvm {
/// Registers that this does not apply to simply should set this to null.
///
struct MRegisterDesc {
- const char *Name; // Assembly language name for the register
- const unsigned *AliasSet; // Register Alias Set, described above
- unsigned Flags; // Flags identifying register properties (below)
- unsigned TSFlags; // Target Specific Flags
+ const char *Name; // Assembly language name for the register
+ const unsigned *AliasSet; // Register Alias Set, described above
+ unsigned char SpillSize; // Size of this register in bytes
+ unsigned char SpillAlignment; // Alignment of stack slot for this reg
};
class TargetRegisterClass {
return RegsBegin[i];
}
+ /// contains - Return true if the specified register is included in this
+ /// register class.
+ bool contains(unsigned Reg) const {
+ for (iterator I = begin(), E = end(); I != E; ++I)
+ if (*I == Reg) return true;
+ return false;
+ }
+
/// allocation_order_begin/end - These methods define a range of registers
/// which specify the registers in this class that are valid to register
/// allocate, and the preferred order to allocate them in. For example,
regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
- const TargetRegisterClass **PhysRegClasses; // Reg class for each register
int CallFrameSetupOpcode, CallFrameDestroyOpcode;
protected:
MRegisterInfo(const MRegisterDesc *D, unsigned NR,
/// isPhysicalRegister - Return true if the specified register number is in
/// the physical register namespace.
static bool isPhysicalRegister(unsigned Reg) {
+ assert(Reg && "this is not a register!");
return Reg < FirstVirtualRegister;
}
/// isVirtualRegister - Return true if the specified register number is in
/// the virtual register namespace.
static bool isVirtualRegister(unsigned Reg) {
+ assert(Reg && "this is not a register!");
return Reg >= FirstVirtualRegister;
}
+ /// getAllocatableSet - Returns a bitset indexed by register number
+ /// indicating if a register is allocatable or not.
+ std::vector<bool> getAllocatableSet(MachineFunction &MF) const;
+
const MRegisterDesc &operator[](unsigned RegNo) const {
assert(RegNo < NumRegs &&
"Attempting to access record for invalid register number!");
///
const MRegisterDesc &get(unsigned RegNo) const { return operator[](RegNo); }
- /// getRegClass - Return the register class for the specified physical
- /// register.
- ///
- const TargetRegisterClass *getRegClass(unsigned RegNo) const {
- assert(RegNo < NumRegs && "Register number out of range!");
- assert(PhysRegClasses[RegNo] && "Register is not in a class!");
- return PhysRegClasses[RegNo];
- }
-
/// getAliasSet - Return the set of registers aliased by the specified
/// register, or a null list of there are none. The list returned is zero
/// terminated.
return get(RegNo).Name;
}
+ /// getSpillSize - Return the size in bits required of a stack slot used to
+ /// spill register into.
+ unsigned getSpillSize(unsigned RegNo) const {
+ return get(RegNo).SpillSize;
+ }
+
+ /// getSpillAlignment - Return the alignment required by a stack slot used to
+ /// spill register into.
+ unsigned getSpillAlignment(unsigned RegNo) const {
+ return get(RegNo).SpillAlignment;
+ }
+
/// getNumRegs - Return the number of registers this target has
/// (useful for sizing arrays holding per register information)
unsigned getNumRegs() const {
return NumRegs;
}
+ /// areAliases - Returns true if the two registers alias each other,
+ /// false otherwise
+ bool areAliases(unsigned regA, unsigned regB) const {
+ for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
+ if (*Alias == regB) return true;
+ return false;
+ }
+
virtual const unsigned* getCalleeSaveRegs() const = 0;
return regclass_end()-regclass_begin();
}
- //===--------------------------------------------------------------------===//
- // All basic block modifier functions below return the number of
- // instructions added to (negative if removed from) the basic block
- // passed as their first argument.
- //
- // FIXME: This is only needed because we use a std::vector instead
- // of an ilist to keep MachineBasicBlock instructions. Inserting an
- // instruction to a MachineBasicBlock invalidates all iterators to
- // the basic block. The return value can be used to update an index
- // to the machine basic block instruction vector and circumvent the
- // iterator elimination problem but this is really not needed if we
- // move to a better representation.
- //
-
//===--------------------------------------------------------------------===//
// Interfaces used by the register allocator and stack frame
// manipulation passes to move data around between registers,
// instructions added to (negative if removed from) the basic block.
//
- virtual int storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned SrcReg, int FrameIndex,
- const TargetRegisterClass *RC) const = 0;
-
- virtual int loadRegFromStackSlot(MachineBasicBlock &MBB,
+ virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
- unsigned DestReg, int FrameIndex,
- const TargetRegisterClass *RC) const = 0;
-
- virtual int copyRegToReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned DestReg, unsigned SrcReg,
- const TargetRegisterClass *RC) const = 0;
-
-
- virtual bool canFoldMemoryOperand(MachineInstr* MI, unsigned i) const {
- return false;
- }
-
- virtual int foldMemoryOperand(MachineInstr* MI,
- unsigned i,
- int FrameIndex) const {
+ unsigned SrcReg, int FrameIndex) const = 0;
+
+ virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned DestReg, int FrameIndex) const = 0;
+
+ virtual void copyRegToReg(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned DestReg, unsigned SrcReg,
+ const TargetRegisterClass *RC) const = 0;
+
+
+ /// foldMemoryOperand - Attempt to fold a load or store of the
+ /// specified stack slot into the specified machine instruction for
+ /// the specified operand. If this is possible, a new instruction
+ /// is returned with the specified operand folded, otherwise NULL is
+ /// returned. The client is responsible for removing the old
+ /// instruction and adding the new one in the instruction stream
+ virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
+ unsigned OpNum,
+ int FrameIndex) const {
return 0;
}
/// instructions (but only if the Target is using them). It is responsible
/// for eliminating these instructions, replacing them with concrete
/// instructions. This method need only be implemented if using call frame
- /// setup/destroy pseudo instructions. The return value is the number of
- /// instructions added to (negative if removed from) the basic block.
+ /// setup/destroy pseudo instructions.
///
virtual void
eliminateCallFramePseudoInstr(MachineFunction &MF,
/// finished product. The return value is the number of instructions
/// added to (negative if removed from) the basic block.
///
- virtual void eliminateFrameIndex(MachineFunction &MF,
- MachineBasicBlock::iterator MI) const = 0;
+ virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI) const = 0;
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
/// the function. The return value is the number of instructions
MachineBasicBlock &MBB) const = 0;
};
+// This is useful when building DenseMaps keyed on virtual registers
+struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
+ unsigned operator()(unsigned Reg) const {
+ return Reg - MRegisterInfo::FirstVirtualRegister;
+ }
+};
+
} // End llvm namespace
#endif
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