//===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file describes an abstract interface used to get information about a
#define LLVM_TARGET_MREGISTERINFO_H
#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/ValueTypes.h"
#include <cassert>
#include <functional>
class Type;
class MachineFunction;
class MachineInstr;
+class TargetRegisterClass;
-/// MRegisterDesc - This record contains all of the information known about a
-/// particular register. The AliasSet field (if not null) contains a pointer to
-/// a Zero terminated array of registers that this register aliases. This is
+/// TargetRegisterDesc - This record contains all of the information known about
+/// a particular register. The AliasSet field (if not null) contains a pointer
+/// to a Zero terminated array of registers that this register aliases. This is
/// needed for architectures like X86 which have AL alias AX alias EAX.
/// Registers that this does not apply to simply should set this to null.
///
-struct MRegisterDesc {
- const char *Name; // Assembly language name for the register
- const unsigned *AliasSet; // Register Alias Set, described above
- unsigned Flags; // Flags identifying register properties (below)
- unsigned TSFlags; // Target Specific Flags
+struct TargetRegisterDesc {
+ const char *Name; // Assembly language name for the register
+ const unsigned *AliasSet; // Register Alias Set, described above
};
class TargetRegisterClass {
typedef const unsigned* const_iterator;
private:
+ const MVT::ValueType VT;
const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
const iterator RegsBegin, RegsEnd;
public:
- TargetRegisterClass(unsigned RS, unsigned Al, iterator RB, iterator RE)
- : RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
+ TargetRegisterClass(MVT::ValueType vt, unsigned RS, unsigned Al, iterator RB, iterator RE)
+ : VT(vt), RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
virtual ~TargetRegisterClass() {} // Allow subclasses
+ /// getType - Return the declared value type for this register class.
+ ///
+ MVT::ValueType getType() const { return VT; }
+
// begin/end - Return all of the registers in this class.
iterator begin() const { return RegsBegin; }
iterator end() const { return RegsEnd; }
return RegsBegin[i];
}
+ /// contains - Return true if the specified register is included in this
+ /// register class.
+ bool contains(unsigned Reg) const {
+ for (iterator I = begin(), E = end(); I != E; ++I)
+ if (*I == Reg) return true;
+ return false;
+ }
+
/// allocation_order_begin/end - These methods define a range of registers
/// which specify the registers in this class that are valid to register
/// allocate, and the preferred order to allocate them in. For example,
virtual iterator allocation_order_end(MachineFunction &MF) const {
return end();
}
-
+
/// getSize - Return the size of the register in bytes, which is also the size
/// MRegisterInfo base class - We assume that the target defines a static array
-/// of MRegisterDesc objects that represent all of the machine registers that
-/// the target has. As such, we simply have to track a pointer to this array so
-/// that we can turn register number into a register descriptor.
+/// of TargetRegisterDesc objects that represent all of the machine registers
+/// that the target has. As such, we simply have to track a pointer to this
+/// array so that we can turn register number into a register descriptor.
///
class MRegisterInfo {
public:
typedef const TargetRegisterClass * const * regclass_iterator;
private:
- const MRegisterDesc *Desc; // Pointer to the descriptor array
+ const TargetRegisterDesc *Desc; // Pointer to the descriptor array
unsigned NumRegs; // Number of entries in the array
regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
- const TargetRegisterClass **PhysRegClasses; // Reg class for each register
int CallFrameSetupOpcode, CallFrameDestroyOpcode;
protected:
- MRegisterInfo(const MRegisterDesc *D, unsigned NR,
+ MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
- int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
+ int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
virtual ~MRegisterInfo();
public:
return Reg >= FirstVirtualRegister;
}
- const MRegisterDesc &operator[](unsigned RegNo) const {
+ /// getAllocatableSet - Returns a bitset indexed by register number
+ /// indicating if a register is allocatable or not.
+ std::vector<bool> getAllocatableSet(MachineFunction &MF) const;
+
+ const TargetRegisterDesc &operator[](unsigned RegNo) const {
assert(RegNo < NumRegs &&
"Attempting to access record for invalid register number!");
return Desc[RegNo];
/// Provide a get method, equivalent to [], but more useful if we have a
/// pointer to this object.
///
- const MRegisterDesc &get(unsigned RegNo) const { return operator[](RegNo); }
-
- /// getRegClass - Return the register class for the specified physical
- /// register.
- ///
- const TargetRegisterClass *getRegClass(unsigned RegNo) const {
- assert(RegNo < NumRegs && "Register number out of range!");
- assert(PhysRegClasses[RegNo] && "Register is not in a class!");
- return PhysRegClasses[RegNo];
+ const TargetRegisterDesc &get(unsigned RegNo) const {
+ return operator[](RegNo);
}
/// getAliasSet - Return the set of registers aliased by the specified
/// false otherwise
bool areAliases(unsigned regA, unsigned regB) const {
for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
- if (*Alias == regA) return true;
+ if (*Alias == regB) return true;
return false;
}
+ /// getCalleeSaveRegs - Return a null-terminated list of all of the
+ /// callee-save registers on this target.
virtual const unsigned* getCalleeSaveRegs() const = 0;
+ /// getCalleeSaveRegClasses - Return a null-terminated list of the preferred
+ /// register classes to spill each callee-saved register with. The order and
+ /// length of this list match the getCalleeSaveRegs() list.
+ virtual const TargetRegisterClass* const *getCalleeSaveRegClasses() const = 0;
//===--------------------------------------------------------------------===//
// Register Class Information
return regclass_end()-regclass_begin();
}
- //===--------------------------------------------------------------------===//
- // All basic block modifier functions below return the number of
- // instructions added to (negative if removed from) the basic block
- // passed as their first argument.
- //
- // FIXME: This is only needed because we use a std::vector instead
- // of an ilist to keep MachineBasicBlock instructions. Inserting an
- // instruction to a MachineBasicBlock invalidates all iterators to
- // the basic block. The return value can be used to update an index
- // to the machine basic block instruction vector and circumvent the
- // iterator elimination problem but this is really not needed if we
- // move to a better representation.
- //
-
//===--------------------------------------------------------------------===//
// Interfaces used by the register allocator and stack frame
// manipulation passes to move data around between registers,
// instructions added to (negative if removed from) the basic block.
//
- virtual int storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned SrcReg, int FrameIndex,
- const TargetRegisterClass *RC) const = 0;
-
- virtual int loadRegFromStackSlot(MachineBasicBlock &MBB,
+ virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
- unsigned DestReg, int FrameIndex,
+ unsigned SrcReg, int FrameIndex,
const TargetRegisterClass *RC) const = 0;
- virtual int copyRegToReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned DestReg, unsigned SrcReg,
- const TargetRegisterClass *RC) const = 0;
-
+ virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned DestReg, int FrameIndex,
+ const TargetRegisterClass *RC) const = 0;
+
+ virtual void copyRegToReg(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned DestReg, unsigned SrcReg,
+ const TargetRegisterClass *RC) const = 0;
+
+ /// isLoadFromStackSlot - If the specified machine instruction is a direct
+ /// load from a stack slot, return the virtual or physical register number of
+ /// the destination along with the FrameIndex of the loaded stack slot. If
+ /// not, return 0. This predicate must return false if the instruction has
+ /// any side effects other than loading from the stack slot.
+ virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
+ return 0;
+ }
- /// foldMemoryOperand - If this target supports it, fold a load or store of
- /// the specified stack slot into the specified machine instruction for the
- /// specified operand. If this is possible, the target should perform the
- /// folding and return true, otherwise it should return false. If it folds
- /// the instruction, it is likely that the MachineInstruction the iterator
- /// references has been changed.
- virtual bool foldMemoryOperand(MachineBasicBlock::iterator &MI,
- unsigned OpNum, int FrameIndex) const {
- return false;
+ /// foldMemoryOperand - Attempt to fold a load or store of the
+ /// specified stack slot into the specified machine instruction for
+ /// the specified operand. If this is possible, a new instruction
+ /// is returned with the specified operand folded, otherwise NULL is
+ /// returned. The client is responsible for removing the old
+ /// instruction and adding the new one in the instruction stream
+ virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
+ unsigned OpNum,
+ int FrameIndex) const {
+ return 0;
}
/// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
/// instructions (but only if the Target is using them). It is responsible
/// for eliminating these instructions, replacing them with concrete
/// instructions. This method need only be implemented if using call frame
- /// setup/destroy pseudo instructions. The return value is the number of
- /// instructions added to (negative if removed from) the basic block.
+ /// setup/destroy pseudo instructions.
///
- virtual void
+ virtual void
eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const {
assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
- "eliminateCallFramePseudoInstr must be implemented if using"
- " call frame setup/destroy pseudo instructions!");
+ "eliminateCallFramePseudoInstr must be implemented if using"
+ " call frame setup/destroy pseudo instructions!");
assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
}
/// finished product. The return value is the number of instructions
/// added to (negative if removed from) the basic block.
///
- virtual void eliminateFrameIndex(MachineFunction &MF,
- MachineBasicBlock::iterator MI) const = 0;
+ virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI) const = 0;
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
/// the function. The return value is the number of instructions
MachineBasicBlock &MBB) const = 0;
};
-// This is useful when building DenseMap's keyed on virtual registers
+// This is useful when building DenseMaps keyed on virtual registers
struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
unsigned operator()(unsigned Reg) const {
return Reg - MRegisterInfo::FirstVirtualRegister;
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