#ifndef LLVM_TARGET_MACHINEINSTRINFO_H
#define LLVM_TARGET_MACHINEINSTRINFO_H
-#include "llvm/Target/TargetMachine.h"
-#include "llvm/Support/DataTypes.h"
+#include "Support/NonCopyable.h"
+#include "Support/DataTypes.h"
+#include "llvm/Constant.h"
+#include "llvm/DerivedTypes.h"
+#include <string>
#include <vector>
class MachineInstrDescriptor;
class TmpInstruction;
class MachineInstr;
+class TargetMachine;
class Value;
class Instruction;
+class Function;
+class MachineCodeForInstruction;
+//---------------------------------------------------------------------------
+// Data types used to define information about a single machine instruction
+//---------------------------------------------------------------------------
+typedef int MachineOpCode;
+typedef int OpCodeMask;
typedef int InstrSchedClass;
+const MachineOpCode INVALID_MACHINE_OPCODE = -1;
+
+
// Global variable holding an array of descriptors for machine instructions.
// The actual object needs to be created separately for each target machine.
// This variable is initialized and reset by class MachineInstrInfo.
struct MachineInstrDescriptor {
- string opCodeString; // Assembly language mnemonic for the opcode.
- int numOperands; // Number of args; -1 if variable #args
- int resultPos; // Position of the result; -1 if no result
+ std::string opCodeString; // Assembly language mnemonic for the opcode.
+ int numOperands; // Number of args; -1 if variable #args
+ int resultPos; // Position of the result; -1 if no result
unsigned int maxImmedConst; // Largest +ve constant in IMMMED field or 0.
- bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
+ bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
// smallest -ve value is -(maxImmedConst+1).
unsigned int numDelaySlots; // Number of delay slots after instruction
unsigned int latency; // Latency in machine cycles
bool isDummyPhiInstr(const MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_DUMMY_PHI_FLAG;
}
-
-
- // delete this later *******
- bool isPhi(const MachineOpCode opCode) const
- { return isDummyPhiInstr(opCode); }
-
bool isPseudoInstr(const MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_PSEUDO_FLAG;
}
-
-
// Check if an instruction can be issued before its operands are ready,
// or if a subsequent instruction that uses its result can be issued
// before the results are ready.
virtual int maxLatency(MachineOpCode opCode) const {
return getDescriptor(opCode).latency;
}
+
+ //
+ // Which operand holds an immediate constant? Returns -1 if none
+ //
+ virtual int getImmedConstantPos(MachineOpCode opCode) const {
+ return -1; // immediate position is machine specific, so say -1 == "none"
+ }
// Check if the specified constant fits in the immediate field
// of this machine instruction
return getDescriptor(opCode).maxImmedConst;
}
+ //-------------------------------------------------------------------------
+ // Queries about representation of LLVM quantities (e.g., constants)
+ //-------------------------------------------------------------------------
+
+ // Test if this type of constant must be loaded from memory into
+ // a register, i.e., cannot be set bitwise in register and cannot
+ // use immediate fields of instructions. Note that this only makes
+ // sense for primitive types.
+ virtual bool ConstantTypeMustBeLoaded(const Constant* CV) const {
+ assert(CV->getType()->isPrimitiveType() || isa<PointerType>(CV->getType()));
+ return !(CV->getType()->isIntegral() || isa<PointerType>(CV->getType()));
+ }
+
+ // Test if this constant may not fit in the immediate field of the
+ // machine instructions (probably) generated for this instruction.
+ //
+ virtual bool ConstantMayNotFitInImmedField(const Constant* CV,
+ const Instruction* I) const {
+ return true; // safe but very conservative
+ }
+
//-------------------------------------------------------------------------
// Code generation support for creating individual machine instructions
//-------------------------------------------------------------------------
-
+
+ // Get certain common op codes for the current target. this and all the
+ // Create* methods below should be moved to a machine code generation class
+ //
+ virtual MachineOpCode getNOPOpCode() const = 0;
+
// Create an instruction sequence to put the constant `val' into
- // the virtual register `dest'. `val' may be a ConstPoolVal or a
+ // the virtual register `dest'. `val' may be a Constant or a
// GlobalValue, viz., the constant address of a global variable or function.
- // The generated instructions are returned in `minstrVec'.
- // Any temp. registers (TmpInstruction) created are returned in `tempVec'.
+ // The generated instructions are returned in `mvec'.
+ // Any temp. registers (TmpInstruction) created are recorded in mcfi.
+ // Symbolic constants or constants that must be accessed from memory
+ // are added to the constant pool via MachineCodeForMethod::get(F).
//
- virtual void CreateCodeToLoadConst(Value* val,
+ virtual void CreateCodeToLoadConst(const TargetMachine& target,
+ Function* F,
+ Value* val,
Instruction* dest,
- vector<MachineInstr*>& minstrVec,
- vector<TmpInstruction*>& temps) const =0;
-
+ std::vector<MachineInstr*>& mvec,
+ MachineCodeForInstruction& mcfi) const=0;
+
// Create an instruction sequence to copy an integer value `val'
// to a floating point value `dest' by copying to memory and back.
// val must be an integral type. dest must be a Float or Double.
- // The generated instructions are returned in `minstrVec'.
- // Any temp. registers (TmpInstruction) created are returned in `tempVec'.
+ // The generated instructions are returned in `mvec'.
+ // Any temp. registers (TmpInstruction) created are recorded in mcfi.
+ // Any stack space required is allocated via mcff.
//
- virtual void CreateCodeToCopyIntToFloat(Method* method,
- Value* val,
- Instruction* dest,
- vector<MachineInstr*>& minstrVec,
- vector<TmpInstruction*>& tempVec,
- TargetMachine& target) const = 0;
+ virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
+ Function* F,
+ Value* val,
+ Instruction* dest,
+ std::vector<MachineInstr*>& mvec,
+ MachineCodeForInstruction& mcfi)const=0;
// Similarly, create an instruction sequence to copy an FP value
// `val' to an integer value `dest' by copying to memory and back.
- // See the previous function for information about return values.
+ // The generated instructions are returned in `mvec'.
+ // Any temp. registers (TmpInstruction) created are recorded in mcfi.
+ // Any stack space required is allocated via mcff.
//
- virtual void CreateCodeToCopyFloatToInt(Method* method,
- Value* val,
- Instruction* dest,
- vector<MachineInstr*>& minstrVec,
- vector<TmpInstruction*>& tempVec,
- TargetMachine& target) const = 0;
-
-
- // create copy instruction(s)
- virtual void
- CreateCopyInstructionsByType(const TargetMachine& target,
- Value* src,
- Instruction* dest,
- vector<MachineInstr*>& minstrVec) const = 0;
-
+ virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
+ Function* F,
+ Value* val,
+ Instruction* dest,
+ std::vector<MachineInstr*>& mvec,
+ MachineCodeForInstruction& mcfi)const=0;
+
+ // Create instruction(s) to copy src to dest, for arbitrary types
+ // The generated instructions are returned in `mvec'.
+ // Any temp. registers (TmpInstruction) created are recorded in mcfi.
+ // Any stack space required is allocated via mcff.
+ //
+ virtual void CreateCopyInstructionsByType(const TargetMachine& target,
+ Function* F,
+ Value* src,
+ Instruction* dest,
+ std::vector<MachineInstr*>& mvec,
+ MachineCodeForInstruction& mcfi)const=0;
+ // Create instruction sequence to produce a sign-extended register value
+ // from an arbitrary sized value (sized in bits, not bytes).
+ // The generated instructions are appended to `mvec'.
+ // Any temp. registers (TmpInstruction) created are recorded in mcfi.
+ // Any stack space required is allocated via mcff.
+ //
+ virtual void CreateSignExtensionInstructions(const TargetMachine& target,
+ Function* F,
+ Value* srcVal,
+ unsigned int srcSizeInBits,
+ Value* dest,
+ std::vector<MachineInstr*>& mvec,
+ MachineCodeForInstruction& mcfi) const=0;
+ // Create instruction sequence to produce a zero-extended register value
+ // from an arbitrary sized value (sized in bits, not bytes).
+ // The generated instructions are appended to `mvec'.
+ // Any temp. registers (TmpInstruction) created are recorded in mcfi.
+ // Any stack space required is allocated via mcff.
+ //
+ virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
+ Function* F,
+ Value* srcVal,
+ unsigned int srcSizeInBits,
+ Value* dest,
+ std::vector<MachineInstr*>& mvec,
+ MachineCodeForInstruction& mcfi) const=0;
};
#endif
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