class RegisterClass; // Forward def
+// SubRegIndex - Use instances of SubRegIndex to identify subregisters.
+class SubRegIndex {
+ string Namespace = "";
+}
+
// Register - You should define one instance of this class for each register
// in the target machine. String n will become the "name" of the register.
class Register<string n> {
// not [AX, AH, AL].
list<Register> SubRegs = [];
+ // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
+ // to address it. Sub-sub-register indices are automatically inherited from
+ // SubRegs.
+ list<SubRegIndex> SubRegIndices = [];
+
+ // CompositeIndices - Specify subreg indices that don't correspond directly to
+ // a register in SubRegs and are not inherited. The following formats are
+ // supported:
+ //
+ // (a) Identity - Reg:a == Reg
+ // (a b) Alias - Reg:a == Reg:b
+ // (a b,c) Composite - Reg:a == (Reg:b):c
+ //
+ // This can be used to disambiguate a sub-sub-register that exists in more
+ // than one subregister and other weird stuff.
+ list<dag> CompositeIndices = [];
+
// DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
// These values can be determined by locating the <target>.h file in the
// directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
let SubRegs = subregs;
}
-// SubRegSet - This can be used to define a specific mapping of registers to
-// indices, for use as named subregs of a particular physical register. Each
-// register in 'subregs' becomes an addressable subregister at index 'n' of the
-// corresponding register in 'regs'.
-class SubRegSet<int n, list<Register> regs, list<Register> subregs> {
- int index = n;
-
- list<Register> From = regs;
- list<Register> To = subregs;
-}
-
// RegisterClass - Now that all of the registers are defined, and aliases
// between registers are defined, specify which registers belong to which
// register classes. This also defines the default allocation order of
//
list<Register> MemberList = regList;
- // SubClassList - Specify which register classes correspond to subregisters
- // of this class. The order should be by subregister set index.
- list<RegisterClass> SubRegClassList = [];
+ // SubRegClasses - Specify the register class of subregisters as a list of
+ // dags: (RegClass SubRegIndex, SubRegindex, ...)
+ list<dag> SubRegClasses = [];
// MethodProtos/MethodBodies - These members can be used to insert arbitrary
// code into a generated register class. The normal usage of this is to
//===----------------------------------------------------------------------===//
// DwarfRegNum - This class provides a mapping of the llvm register enumeration
// to the register numbering used by gcc and gdb. These values are used by a
-// debug information writer (ex. DwarfWriter) to describe where values may be
-// located during execution.
+// debug information writer to describe where values may be located during
+// execution.
class DwarfRegNum<list<int> Numbers> {
// DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
// These values can be determined by locating the <target>.h file in the
// purposes.
bit isCodeGenOnly = 0;
+ // Is this instruction a pseudo instruction for use by the assembler parser.
+ bit isAsmParserOnly = 0;
+
InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
-
+
/// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
/// be encoded into the output machineinstr.
string DisableEncoding = "";
+
+ /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
+ bits<64> TSFlags = 0;
}
/// Predicates - These are extra conditionals which are turned into instruction
/// The name to use for this class, which should be usable as an enum value.
string Name = ?;
- /// The super class of this operand.
- AsmOperandClass SuperClass = ?;
+ /// The super classes of this operand.
+ list<AsmOperandClass> SuperClasses = [];
/// The name of the method on the target specific operand to call to test
/// whether the operand is an instance of this class. If not set, this will
// in. Match classes are used to define the order in which instructions are
// match, to ensure that which instructions gets matched is deterministic.
//
- // The target specific parser must be able to classify an parsed operand
- // into a unique class, which does not partially overlap with any other
- // classes. It can match a subset of some other class, in which case
- // ParserMatchSuperClass should be set to the name of that class.
+ // The target specific parser must be able to classify an parsed operand into
+ // a unique class, which does not partially overlap with any other classes. It
+ // can match a subset of some other class, in which case the AsmOperandClass
+ // should declare the other operand as one of its super classes.
AsmOperandClass ParserMatchClass = ImmAsmOperand;
}
// which are global to the target machine.
//
class InstrInfo {
- // If the target wants to associate some target-specific information with each
- // instruction, it should provide these two lists to indicate how to assemble
- // the target specific information into the 32 bits available.
- //
- list<string> TSFlagsFields = [];
- list<int> TSFlagsShifts = [];
-
// Target can specify its instructions in either big or little-endian formats.
// For instance, while both Sparc and PowerPC are big-endian platforms, the
// Sparc manual specifies its instructions in the format [31..0] (big), while
// Standard Pseudo Instructions.
let isCodeGenOnly = 1 in {
def PHI : Instruction {
- let OutOperandList = (ops);
- let InOperandList = (ops variable_ops);
+ let OutOperandList = (outs);
+ let InOperandList = (ins variable_ops);
let AsmString = "PHINODE";
let Namespace = "TargetOpcode";
}
def INLINEASM : Instruction {
- let OutOperandList = (ops);
- let InOperandList = (ops variable_ops);
+ let OutOperandList = (outs);
+ let InOperandList = (ins variable_ops);
let AsmString = "";
let Namespace = "TargetOpcode";
}
def DBG_LABEL : Instruction {
- let OutOperandList = (ops);
- let InOperandList = (ops i32imm:$id);
+ let OutOperandList = (outs);
+ let InOperandList = (ins i32imm:$id);
let AsmString = "";
let Namespace = "TargetOpcode";
let hasCtrlDep = 1;
let isNotDuplicable = 1;
}
def EH_LABEL : Instruction {
- let OutOperandList = (ops);
- let InOperandList = (ops i32imm:$id);
+ let OutOperandList = (outs);
+ let InOperandList = (ins i32imm:$id);
let AsmString = "";
let Namespace = "TargetOpcode";
let hasCtrlDep = 1;
let isNotDuplicable = 1;
}
def GC_LABEL : Instruction {
- let OutOperandList = (ops);
- let InOperandList = (ops i32imm:$id);
+ let OutOperandList = (outs);
+ let InOperandList = (ins i32imm:$id);
let AsmString = "";
let Namespace = "TargetOpcode";
let hasCtrlDep = 1;
let isNotDuplicable = 1;
}
def KILL : Instruction {
- let OutOperandList = (ops);
- let InOperandList = (ops variable_ops);
+ let OutOperandList = (outs);
+ let InOperandList = (ins variable_ops);
let AsmString = "";
let Namespace = "TargetOpcode";
let neverHasSideEffects = 1;
}
def EXTRACT_SUBREG : Instruction {
- let OutOperandList = (ops unknown:$dst);
- let InOperandList = (ops unknown:$supersrc, i32imm:$subidx);
+ let OutOperandList = (outs unknown:$dst);
+ let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
let AsmString = "";
let Namespace = "TargetOpcode";
let neverHasSideEffects = 1;
}
def INSERT_SUBREG : Instruction {
- let OutOperandList = (ops unknown:$dst);
- let InOperandList = (ops unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
+ let OutOperandList = (outs unknown:$dst);
+ let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
let AsmString = "";
let Namespace = "TargetOpcode";
let neverHasSideEffects = 1;
let Constraints = "$supersrc = $dst";
}
def IMPLICIT_DEF : Instruction {
- let OutOperandList = (ops unknown:$dst);
- let InOperandList = (ops);
+ let OutOperandList = (outs unknown:$dst);
+ let InOperandList = (ins);
let AsmString = "";
let Namespace = "TargetOpcode";
let neverHasSideEffects = 1;
let isAsCheapAsAMove = 1;
}
def SUBREG_TO_REG : Instruction {
- let OutOperandList = (ops unknown:$dst);
- let InOperandList = (ops unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
+ let OutOperandList = (outs unknown:$dst);
+ let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
let AsmString = "";
let Namespace = "TargetOpcode";
let neverHasSideEffects = 1;
}
def COPY_TO_REGCLASS : Instruction {
- let OutOperandList = (ops unknown:$dst);
- let InOperandList = (ops unknown:$src, i32imm:$regclass);
+ let OutOperandList = (outs unknown:$dst);
+ let InOperandList = (ins unknown:$src, i32imm:$regclass);
let AsmString = "";
let Namespace = "TargetOpcode";
let neverHasSideEffects = 1;
let isAsCheapAsAMove = 1;
}
def DBG_VALUE : Instruction {
- let OutOperandList = (ops);
- let InOperandList = (ops variable_ops);
+ let OutOperandList = (outs);
+ let InOperandList = (ins variable_ops);
let AsmString = "DBG_VALUE";
let Namespace = "TargetOpcode";
let isAsCheapAsAMove = 1;
}
+
+def REG_SEQUENCE : Instruction {
+ let OutOperandList = (outs unknown:$dst);
+ let InOperandList = (ins variable_ops);
+ let AsmString = "";
+ let Namespace = "TargetOpcode";
+ let neverHasSideEffects = 1;
+ let isAsCheapAsAMove = 1;
+}
}
//===----------------------------------------------------------------------===//
-// AsmParser - This class can be implemented by targets that wish to implement
+// AsmParser - This class can be implemented by targets that wish to implement
// .s file parsing.
//
-// Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
+// Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
// syntax on X86 for example).
//
class AsmParser {
// class. Generated AsmParser classes are always prefixed with the target
// name.
string AsmParserClassName = "AsmParser";
-
+
+ // AsmParserInstCleanup - If non-empty, this is the name of a custom function on the
+ // AsmParser class to call on every matched instruction. This can be used to
+ // perform target specific instruction post-processing.
+ string AsmParserInstCleanup = "";
+
+ // MatchInstructionName - The name of the instruction matching function to
+ // generate.
+ string MatchInstructionName = "MatchInstruction";
+
// Variant - AsmParsers can be of multiple different variants. Variants are
- // used to support targets that need to parser multiple formats for the
+ // used to support targets that need to parser multiple formats for the
// assembly language.
int Variant = 0;