class RegisterClass; // Forward def
// SubRegIndex - Use instances of SubRegIndex to identify subregisters.
-class SubRegIndex<int size = -1, int offset = 0> {
+class SubRegIndex<int size, int offset = 0> {
string Namespace = "";
// Size - Size (in bits) of the sub-registers represented by this index.
int Size = size;
// Offset - Offset of the first bit that is part of this sub-register index.
+ // Set it to -1 if the same index is used to represent sub-registers that can
+ // be at different offsets (for example when using an index to access an
+ // element in a register tuple).
int Offset = offset;
// ComposedOf - A list of two SubRegIndex instances, [A, B].
// ComposedSubRegIndex - A sub-register that is the result of composing A and B.
// Offset is set to the sum of A and B's Offsets. Size is set to B's Size.
class ComposedSubRegIndex<SubRegIndex A, SubRegIndex B>
- : SubRegIndex<B.Size, -1> {
+ : SubRegIndex<B.Size, !if(!eq(A.Offset, -1), -1,
+ !if(!eq(B.Offset, -1), -1,
+ !add(A.Offset, B.Offset)))> {
// See SubRegIndex.
let ComposedOf = [A, B];
}
bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
+ bit isRegSequence = 0; // Is this instruction a kind of reg sequence?
+ // If so, make sure to override
+ // TargetInstrInfo::getRegSequenceLikeInputs.
bit isPseudo = 0; // Is this instruction a pseudo-instruction?
// If so, won't have encoding information for
// the [MC]CodeEmitter stuff.
+ bit isExtractSubreg = 0; // Is this instruction a kind of extract subreg?
+ // If so, make sure to override
+ // TargetInstrInfo::getExtractSubregLikeInputs.
+ bit isInsertSubreg = 0; // Is this instruction a kind of insert subreg?
+ // If so, make sure to override
+ // TargetInstrInfo::getInsertSubregLikeInputs.
// Side effect flags - When set, the flags have these meanings:
//
string TwoOperandAliasConstraint = "";
///@}
+
+ /// UseNamedOperandTable - If set, the operand indices of this instruction
+ /// can be queried via the getNamedOperandIdx() function which is generated
+ /// by TableGen.
+ bit UseNamedOperandTable = 0;
}
/// PseudoInstExpansion - Expansion information for a pseudo-instruction.
string PrintMethod = "printOperand";
string EncoderMethod = "";
string DecoderMethod = "";
- string AsmOperandLowerMethod = ?;
string OperandType = "OPERAND_UNKNOWN";
dag MIOperandInfo = (ops);
+ // MCOperandPredicate - Optionally, a code fragment operating on
+ // const MCOperand &MCOp, and returning a bool, to indicate if
+ // the value of MCOp is valid for the specific subclass of Operand
+ code MCOperandPredicate;
+
// ParserMatchClass - The "match class" that operands of this type fit
// in. Match classes are used to define the order in which instructions are
// match, to ensure that which instructions gets matched is deterministic.
///
def zero_reg;
+/// All operands which the MC layer classifies as predicates should inherit from
+/// this class in some manner. This is already handled for the most commonly
+/// used PredicateOperand, but may be useful in other circumstances.
+class PredicateOp;
+
/// OperandWithDefaultOps - This Operand class can be used as the parent class
/// for an Operand that needs to be initialized with a default value if
/// no value is supplied in a pattern. This class can be used to simplify the
/// AlwaysVal specifies the value of this predicate when set to "always
/// execute".
class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
- : OperandWithDefaultOps<ty, AlwaysVal> {
+ : OperandWithDefaultOps<ty, AlwaysVal>, PredicateOp {
let MIOperandInfo = OpTypes;
}
//
// This option is a temporary migration help. It will go away.
bit guessInstructionProperties = 1;
+
+ // TableGen's instruction encoder generator has support for matching operands
+ // to bit-field variables both by name and by position. While matching by
+ // name is preferred, this is currently not possible for complex operands,
+ // and some targets still reply on the positional encoding rules. When
+ // generating a decoder for such targets, the positional encoding rules must
+ // be used by the decoder generator as well.
+ //
+ // This option is temporary; it will go away once the TableGen decoder
+ // generator has better support for complex operands and targets have
+ // migrated away from using positionally encoded operands.
+ bit decodePositionallyEncodedOperands = 0;
+
+ // When set, this indicates that there will be no overlap between those
+ // operands that are matched by ordering (positional operands) and those
+ // matched by name.
+ //
+ // This option is temporary; it will go away once the TableGen decoder
+ // generator has better support for complex operands and targets have
+ // migrated away from using positionally encoded operands.
+ bit noNamedPositionallyEncodedOperands = 0;
}
// Standard Pseudo Instructions.
let AsmString = "";
let neverHasSideEffects = 1; // Note side effect is encoded in an operand.
}
-def PROLOG_LABEL : Instruction {
+def CFI_INSTRUCTION : Instruction {
let OutOperandList = (outs);
let InOperandList = (ins i32imm:$id);
let AsmString = "";
}
def REG_SEQUENCE : Instruction {
let OutOperandList = (outs unknown:$dst);
- let InOperandList = (ins variable_ops);
+ let InOperandList = (ins unknown:$supersrc, variable_ops);
let AsmString = "";
let neverHasSideEffects = 1;
let isAsCheapAsAMove = 1;
let AsmString = "LIFETIME_END";
let neverHasSideEffects = 1;
}
+def STACKMAP : Instruction {
+ let OutOperandList = (outs);
+ let InOperandList = (ins i64imm:$id, i32imm:$nbytes, variable_ops);
+ let isCall = 1;
+ let mayLoad = 1;
+ let usesCustomInserter = 1;
+}
+def PATCHPOINT : Instruction {
+ let OutOperandList = (outs unknown:$dst);
+ let InOperandList = (ins i64imm:$id, i32imm:$nbytes, unknown:$callee,
+ i32imm:$nargs, i32imm:$cc, variable_ops);
+ let isCall = 1;
+ let mayLoad = 1;
+ let usesCustomInserter = 1;
+}
+def LOAD_STACK_GUARD : Instruction {
+ let OutOperandList = (outs ptr_rc:$dst);
+ let InOperandList = (ins);
+ let mayLoad = 1;
+ bit isReMaterializable = 1;
+ let hasSideEffects = 0;
+ bit isPseudo = 1;
+}
}
//===----------------------------------------------------------------------===//
// ShouldEmitMatchRegisterName - Set to false if the target needs a hand
// written register name matcher
bit ShouldEmitMatchRegisterName = 1;
+
+ /// Does the instruction mnemonic allow '.'
+ bit MnemonicContainsDot = 0;
}
def DefaultAsmParser : AsmParser;
/// InstAlias - This defines an alternate assembly syntax that is allowed to
/// match an instruction that has a different (more canonical) assembly
/// representation.
-class InstAlias<string Asm, dag Result, bit Emit = 0b1> {
+class InstAlias<string Asm, dag Result, int Emit = 1> {
string AsmString = Asm; // The .s format to match the instruction with.
dag ResultInst = Result; // The MCInst to generate.
- bit EmitAlias = Emit; // Emit the alias instead of what's aliased.
+
+ // This determines which order the InstPrinter detects aliases for
+ // printing. A larger value makes the alias more likely to be
+ // emitted. The Instruction's own definition is notionally 0.5, so 0
+ // disables printing and 1 enables it if there are no conflicting aliases.
+ int EmitPriority = Emit;
// Predicates - Predicates that must be true for this to match.
list<Predicate> Predicates = [];
// AsmWriterClassName - This specifies the suffix to use for the asmwriter
// class. Generated AsmWriter classes are always prefixed with the target
// name.
- string AsmWriterClassName = "AsmPrinter";
+ string AsmWriterClassName = "InstPrinter";
// Variant - AsmWriters can be of multiple different variants. Variants are
// used to support targets that need to emit assembly code in ways that are
// == 1, will expand to "y".
int Variant = 0;
-
- // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar
- // layout, the asmwriter can actually generate output in this columns (in
- // verbose-asm mode). These two values indicate the width of the first column
- // (the "opcode" area) and the width to reserve for subsequent operands. When
- // verbose asm mode is enabled, operands will be indented to respect this.
- int FirstOperandColumn = -1;
-
// OperandSpacing - Space between operand columns.
int OperandSpacing = -1;
-
- // isMCAsmWriter - Is this assembly writer for an MC emitter? This controls
- // generation of the printInstruction() method. For MC printers, it takes
- // an MCInstr* operand, otherwise it takes a MachineInstr*.
- bit isMCAsmWriter = 0;
}
def DefaultAsmWriter : AsmWriter;
list<SubtargetFeature> Implies = i;
}
+/// Specifies a Subtarget feature that this instruction is deprecated on.
+class Deprecated<SubtargetFeature dep> {
+ SubtargetFeature DeprecatedFeatureMask = dep;
+}
+
+/// A custom predicate used to determine if an instruction is
+/// deprecated or not.
+class ComplexDeprecationPredicate<string dep> {
+ string ComplexDeprecationPredicate = dep;
+}
+
//===----------------------------------------------------------------------===//
// Processor chip sets - These values represent each of the chip sets supported
// by the scheduler. Each Processor definition requires corresponding