Use a better name for the label relocations while emitting them for Jump Tables

[oota-llvm.git] / include / llvm / Target / Target.td

diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td
index 4af108925fc9da534a01e0ca493e58154b027c23..94ae94a14b57e2808b683a46c03e3d770a13cf33 100644 (file)
--- a/include/llvm/Target/Target.td
+++ b/include/llvm/Target/Target.td
@@ -274,6 +274,7 @@ def unknown;
 class Operand<ValueType ty> {
   ValueType Type = ty;
   string PrintMethod = "printOperand";
+  string AsmOperandLowerMethod = ?;
   dag MIOperandInfo = (ops);
 }
 
@@ -301,8 +302,8 @@ class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
 }
 
 /// OptionalDefOperand - This is used to define a optional definition operand
-/// for an instruction. DefaultOps is the register the operand represents if none
-/// is supplied, e.g. zero_reg.
+/// for an instruction. DefaultOps is the register the operand represents if
+/// none is supplied, e.g. zero_reg.
 class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
   : Operand<ty> {
   let MIOperandInfo = OpTypes;
@@ -326,11 +327,6 @@ class InstrInfo {
   // Sparc manual specifies its instructions in the format [31..0] (big), while
   // PowerPC specifies them using the format [0..31] (little).
   bit isLittleEndianEncoding = 0;
-
-  // Targets that can support the HasI1 argument on ADDC and ADDE, rather than
-  // Flag, have this bit set.  This is transitional and should go away when all
-  // targets have been switched over.
-  bit supportsHasI1 = 0;
 }
 
 // Standard Instructions.