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[oota-llvm.git] / include / llvm / Target / TargetInstrInfo.h

diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h
index fcd0016ca09f99db22a6cd0235ea3cca7b7ed4ff..17acacec41d9b209187cdb06c283f3a5313117b4 100644 (file)
--- a/include/llvm/Target/TargetInstrInfo.h
+++ b/include/llvm/Target/TargetInstrInfo.h
@@ -101,7 +101,8 @@ public:
   /// the destination along with the FrameIndex of the loaded stack slot.  If
   /// not, return 0.  This predicate must return 0 if the instruction has
   /// any side effects other than loading from the stack slot.
-  virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
+  virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
+                                       int &FrameIndex) const {
     return 0;
   }
   
@@ -110,7 +111,8 @@ public:
   /// the source reg along with the FrameIndex of the loaded stack slot.  If
   /// not, return 0.  This predicate must return 0 if the instruction has
   /// any side effects other than storing to the stack slot.
-  virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
+  virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
+                                      int &FrameIndex) const {
     return 0;
   }
 
@@ -127,7 +129,7 @@ public:
   /// from the argument area of a function if it does not change.  This should
   /// only return true of *all* loads the instruction does are invariant (if it
   /// does multiple loads).
-  virtual bool isInvariantLoad(MachineInstr *MI) const {
+  virtual bool isInvariantLoad(const MachineInstr *MI) const {
     return false;
   }
   
@@ -200,7 +202,7 @@ public:
   }
   
   /// RemoveBranch - Remove the branching code at the end of the specific MBB.
-  /// this is only invoked in cases where AnalyzeBranch returns success. It
+  /// This is only invoked in cases where AnalyzeBranch returns success. It
   /// returns the number of instructions that were removed.
   virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
     assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 
@@ -220,7 +222,9 @@ public:
     return 0;
   }
   
-  /// copyRegToReg - Add a copy between a pair of registers
+  /// copyRegToReg - Emit instructions to copy between a pair of registers. It
+  /// returns false if the target does not how to copy between the specified
+  /// registers.
   virtual bool copyRegToReg(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MI,
                             unsigned DestReg, unsigned SrcReg,
@@ -230,6 +234,11 @@ public:
     return false;
   }
   
+  /// storeRegToStackSlot - Store the specified register of the given register
+  /// class to the specified stack frame index. The store instruction is to be
+  /// added to the given machine basic block before the specified machine
+  /// instruction. If isKill is true, the register operand is the last use and
+  /// must be marked kill.
   virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
                                    MachineBasicBlock::iterator MI,
                                    unsigned SrcReg, bool isKill, int FrameIndex,
@@ -237,6 +246,11 @@ public:
     assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
   }
 
+  /// storeRegToAddr - Store the specified register of the given register class
+  /// to the specified address. The store instruction is to be added to the
+  /// given machine basic block before the specified machine instruction. If
+  /// isKill is true, the register operand is the last use and must be marked
+  /// kill.
   virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
                               SmallVectorImpl<MachineOperand> &Addr,
                               const TargetRegisterClass *RC,
@@ -244,6 +258,10 @@ public:
     assert(0 && "Target didn't implement TargetInstrInfo::storeRegToAddr!");
   }
 
+  /// loadRegFromStackSlot - Load the specified register of the given register
+  /// class from the specified stack frame index. The load instruction is to be
+  /// added to the given machine basic block before the specified machine
+  /// instruction.
   virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
                                     MachineBasicBlock::iterator MI,
                                     unsigned DestReg, int FrameIndex,
@@ -251,6 +269,9 @@ public:
     assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
   }
 
+  /// loadRegFromAddr - Load the specified register of the given register class
+  /// class from the specified address. The load instruction is to be added to
+  /// the given machine basic block before the specified machine instruction.
   virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
                                SmallVectorImpl<MachineOperand> &Addr,
                                const TargetRegisterClass *RC,
@@ -286,7 +307,7 @@ public:
   /// stream.
   virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
                                           MachineInstr* MI,
-                                          SmallVectorImpl<unsigned> &Ops,
+                                          const SmallVectorImpl<unsigned> &Ops,
                                           int FrameIndex) const {
     return 0;
   }
@@ -296,7 +317,7 @@ public:
   /// stack slot.
   virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
                                           MachineInstr* MI,
-                                          SmallVectorImpl<unsigned> &Ops,
+                                          const SmallVectorImpl<unsigned> &Ops,
                                           MachineInstr* LoadMI) const {
     return 0;
   }
@@ -304,8 +325,8 @@ public:
   /// canFoldMemoryOperand - Returns true if the specified load / store is
   /// folding is possible.
   virtual
-  bool canFoldMemoryOperand(MachineInstr *MI,
-                            SmallVectorImpl<unsigned> &Ops) const{
+  bool canFoldMemoryOperand(const MachineInstr *MI,
+                            const SmallVectorImpl<unsigned> &Ops) const {
     return false;
   }
 
@@ -336,7 +357,7 @@ public:
   /// fall-through into its successor block.  This is primarily used when a
   /// branch is unanalyzable.  It is useful for things like unconditional
   /// indirect branches (jump tables).
-  virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
+  virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
     return false;
   }
   
@@ -388,6 +409,13 @@ public:
     return false;
   }
 
+  /// IgnoreRegisterClassBarriers - Returns true if pre-register allocation
+  /// live interval splitting pass should ignore barriers of the specified
+  /// register class.
+  virtual bool IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const{
+    return true;
+  }
+
   /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
   /// values.
   virtual const TargetRegisterClass *getPointerRegClass() const {
@@ -406,7 +434,6 @@ public:
   /// GetFunctionSizeInBytes - Returns the size of the specified MachineFunction.
   /// 
   virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0;
-
 };
 
 /// TargetInstrInfoImpl - This is the default implementation of