-//===-- llvm/Target/MachineInstrInstrInfo.h - Instruction Infor ---*-C++-*-===//
+//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
//
// This file describes the target machine instructions to the code generator.
//
//===----------------------------------------------------------------------===//
-#ifndef LLVM_TARGET_MACHINEINSTRINFO_H
-#define LLVM_TARGET_MACHINEINSTRINFO_H
+#ifndef LLVM_TARGET_TARGETINSTRINFO_H
+#define LLVM_TARGET_TARGETINSTRINFO_H
#include "Support/DataTypes.h"
#include <vector>
+#include <cassert>
-class MachineInstrDescriptor;
class MachineInstr;
class TargetMachine;
class Value;
+class Type;
class Instruction;
class Constant;
class Function;
//---------------------------------------------------------------------------
-// struct MachineInstrDescriptor:
+// struct TargetInstrDescriptor:
// Predefined information about each machine instruction.
// Designed to initialized statically.
-//
-// class MachineInstructionInfo
-// Interface to description of machine instructions
-//
-//---------------------------------------------------------------------------
+//
-const unsigned M_NOP_FLAG = 1 << 0;
-const unsigned M_BRANCH_FLAG = 1 << 1;
-const unsigned M_CALL_FLAG = 1 << 2;
-const unsigned M_RET_FLAG = 1 << 3;
-const unsigned M_ARITH_FLAG = 1 << 4;
-const unsigned M_CC_FLAG = 1 << 6;
-const unsigned M_LOGICAL_FLAG = 1 << 6;
-const unsigned M_INT_FLAG = 1 << 7;
-const unsigned M_FLOAT_FLAG = 1 << 8;
-const unsigned M_CONDL_FLAG = 1 << 9;
-const unsigned M_LOAD_FLAG = 1 << 10;
-const unsigned M_PREFETCH_FLAG = 1 << 11;
-const unsigned M_STORE_FLAG = 1 << 12;
-const unsigned M_DUMMY_PHI_FLAG = 1 << 13;
-const unsigned M_PSEUDO_FLAG = 1 << 14; // Pseudo instruction
+const unsigned M_NOP_FLAG = 1 << 0;
+const unsigned M_BRANCH_FLAG = 1 << 1;
+const unsigned M_CALL_FLAG = 1 << 2;
+const unsigned M_RET_FLAG = 1 << 3;
+const unsigned M_ARITH_FLAG = 1 << 4;
+const unsigned M_CC_FLAG = 1 << 6;
+const unsigned M_LOGICAL_FLAG = 1 << 6;
+const unsigned M_INT_FLAG = 1 << 7;
+const unsigned M_FLOAT_FLAG = 1 << 8;
+const unsigned M_CONDL_FLAG = 1 << 9;
+const unsigned M_LOAD_FLAG = 1 << 10;
+const unsigned M_PREFETCH_FLAG = 1 << 11;
+const unsigned M_STORE_FLAG = 1 << 12;
+const unsigned M_DUMMY_PHI_FLAG = 1 << 13;
+const unsigned M_PSEUDO_FLAG = 1 << 14; // Pseudo instruction
// 3-addr instructions which really work like 2-addr ones, eg. X86 add/sub
-const unsigned M_2_ADDR_FLAG = 1 << 15;
+const unsigned M_2_ADDR_FLAG = 1 << 15;
+
+// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
+// block? Typically this is things like return and branch instructions.
+// Various passes use this to insert code into the bottom of a basic block, but
+// before control flow occurs.
+const unsigned M_TERMINATOR_FLAG = 1 << 16;
-struct MachineInstrDescriptor {
+struct TargetInstrDescriptor {
const char * Name; // Assembly language mnemonic for the opcode.
int numOperands; // Number of args; -1 if variable #args
int resultPos; // Position of the result; -1 if no result
};
-class MachineInstrInfo {
- const MachineInstrDescriptor* desc; // raw array to allow static init'n
- unsigned descSize; // number of entries in the desc array
- unsigned numRealOpCodes; // number of non-dummy op codes
+//---------------------------------------------------------------------------
+///
+/// TargetInstrInfo - Interface to description of machine instructions
+///
+class TargetInstrInfo {
+ const TargetInstrDescriptor* desc; // raw array to allow static init'n
+ unsigned descSize; // number of entries in the desc array
+ unsigned numRealOpCodes; // number of non-dummy op codes
- MachineInstrInfo(const MachineInstrInfo &); // DO NOT IMPLEMENT
- void operator=(const MachineInstrInfo &); // DO NOT IMPLEMENT
+ TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
+ void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
public:
- MachineInstrInfo(const MachineInstrDescriptor *desc, unsigned descSize,
- unsigned numRealOpCodes);
- virtual ~MachineInstrInfo();
+ TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned descSize,
+ unsigned numRealOpCodes);
+ virtual ~TargetInstrInfo();
// Invariant: All instruction sets use opcode #0 as the PHI instruction and
// opcode #1 as the noop instruction.
/// get - Return the machine instruction descriptor that corresponds to the
/// specified instruction opcode.
///
- const MachineInstrDescriptor& get(MachineOpCode opCode) const {
+ const TargetInstrDescriptor& get(MachineOpCode opCode) const {
assert(opCode >= 0 && opCode < (int)descSize);
return desc[opCode];
}
- /// print - Print out the specified machine instruction in the appropriate
- /// target specific assembly language. If this method is not overridden, the
- /// default implementation uses the crummy machine independant printer.
- ///
- virtual void print(const MachineInstr *MI, std::ostream &O,
- const TargetMachine &TM) const;
-
const char *getName(MachineOpCode opCode) const {
return get(opCode).Name;
}
InstrSchedClass getSchedClass(MachineOpCode opCode) const {
return get(opCode).schedClass;
}
-
+
+ const unsigned *getImplicitUses(MachineOpCode opCode) const {
+ return get(opCode).ImplicitUses;
+ }
+
+ const unsigned *getImplicitDefs(MachineOpCode opCode) const {
+ return get(opCode).ImplicitDefs;
+ }
+
//
// Query instruction class flags according to the machine-independent
// flags listed above.
|| get(opCode).Flags & M_PREFETCH_FLAG
|| get(opCode).Flags & M_STORE_FLAG;
}
- bool isDummyPhiInstr(const MachineOpCode opCode) const {
+ bool isDummyPhiInstr(MachineOpCode opCode) const {
return get(opCode).Flags & M_DUMMY_PHI_FLAG;
}
- bool isPseudoInstr(const MachineOpCode opCode) const {
+ bool isPseudoInstr(MachineOpCode opCode) const {
return get(opCode).Flags & M_PSEUDO_FLAG;
}
- bool isTwoAddrInstr(const MachineOpCode opCode) const {
+ bool isTwoAddrInstr(MachineOpCode opCode) const {
return get(opCode).Flags & M_2_ADDR_FLAG;
}
+ bool isTerminatorInstr(unsigned Opcode) const {
+ return get(Opcode).Flags & M_TERMINATOR_FLAG;
+ }
// Check if an instruction can be issued before its operands are ready,
// or if a subsequent instruction that uses its result can be issued
return true; // safe but very conservative
}
+
+ /// createNOPinstr - returns the target's implementation of NOP, which is
+ /// usually a pseudo-instruction, implemented by a degenerate version of
+ /// another instruction, e.g. X86: xchg ax, ax; SparcV9: sethi g0, 0
+ ///
+ virtual MachineInstr* createNOPinstr() const = 0;
+
+ /// isNOPinstr - not having a special NOP opcode, we need to know if a given
+ /// instruction is interpreted as an `official' NOP instr, i.e., there may be
+ /// more than one way to `do nothing' but only one canonical way to slack off.
+ ///
+ virtual bool isNOPinstr(const MachineInstr &MI) const = 0;
+
//-------------------------------------------------------------------------
// Code generation support for creating individual machine instructions
+ //
+ // WARNING: These methods are Sparc specific
+ //
//-------------------------------------------------------------------------
// Get certain common op codes for the current target. this and all the
// Create* methods below should be moved to a machine code generation class
//
- virtual MachineOpCode getNOPOpCode() const = 0;
+ virtual MachineOpCode getNOPOpCode() const { abort(); }
+
+ // Get the value of an integral constant in the form that must
+ // be put into the machine register. The specified constant is interpreted
+ // as (i.e., converted if necessary to) the specified destination type. The
+ // result is always returned as an uint64_t, since the representation of
+ // int64_t and uint64_t are identical. The argument can be any known const.
+ //
+ // isValidConstant is set to true if a valid constant was found.
+ //
+ virtual uint64_t ConvertConstantToIntType(const TargetMachine &target,
+ const Value *V,
+ const Type *destType,
+ bool &isValidConstant) const {
+ abort();
+ }
// Create an instruction sequence to put the constant `val' into
// the virtual register `dest'. `val' may be a Constant or a
Value* val,
Instruction* dest,
std::vector<MachineInstr*>& mvec,
- MachineCodeForInstruction& mcfi) const=0;
+ MachineCodeForInstruction& mcfi) const {
+ abort();
+ }
// Create an instruction sequence to copy an integer value `val'
// to a floating point value `dest' by copying to memory and back.
// Any temp. registers (TmpInstruction) created are recorded in mcfi.
// Any stack space required is allocated via mcff.
//
- virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
- Function* F,
- Value* val,
- Instruction* dest,
- std::vector<MachineInstr*>& mvec,
- MachineCodeForInstruction& mcfi)const=0;
+ virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
+ Function* F,
+ Value* val,
+ Instruction* dest,
+ std::vector<MachineInstr*>& mvec,
+ MachineCodeForInstruction& MI) const {
+ abort();
+ }
// Similarly, create an instruction sequence to copy an FP value
// `val' to an integer value `dest' by copying to memory and back.
// Any temp. registers (TmpInstruction) created are recorded in mcfi.
// Any stack space required is allocated via mcff.
//
- virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
- Function* F,
- Value* val,
- Instruction* dest,
- std::vector<MachineInstr*>& mvec,
- MachineCodeForInstruction& mcfi)const=0;
+ virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
+ Function* F,
+ Value* val,
+ Instruction* dest,
+ std::vector<MachineInstr*>& mvec,
+ MachineCodeForInstruction& MI) const {
+ abort();
+ }
// Create instruction(s) to copy src to dest, for arbitrary types
// The generated instructions are returned in `mvec'.
// Any stack space required is allocated via mcff.
//
virtual void CreateCopyInstructionsByType(const TargetMachine& target,
- Function* F,
- Value* src,
- Instruction* dest,
- std::vector<MachineInstr*>& mvec,
- MachineCodeForInstruction& mcfi)const=0;
+ Function* F,
+ Value* src,
+ Instruction* dest,
+ std::vector<MachineInstr*>& mvec,
+ MachineCodeForInstruction& MI) const {
+ abort();
+ }
// Create instruction sequence to produce a sign-extended register value
// from an arbitrary sized value (sized in bits, not bytes).
Value* destVal,
unsigned numLowBits,
std::vector<MachineInstr*>& mvec,
- MachineCodeForInstruction& mcfi) const=0;
+ MachineCodeForInstruction& MI) const {
+ abort();
+ }
// Create instruction sequence to produce a zero-extended register value
// from an arbitrary sized value (sized in bits, not bytes).
Value* destVal,
unsigned srcSizeInBits,
std::vector<MachineInstr*>& mvec,
- MachineCodeForInstruction& mcfi) const=0;
+ MachineCodeForInstruction& mcfi) const {
+ abort();
+ }
};
#endif
projects / oota-llvm.git / blobdiff