//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
//
// This file describes the target machine instructions to the code generator.
//
#include "Support/DataTypes.h"
#include <vector>
-#include <assert.h>
+#include <cassert>
+
+namespace llvm {
class MachineInstr;
class TargetMachine;
class Value;
+class Type;
class Instruction;
class Constant;
class Function;
// Data types used to define information about a single machine instruction
//---------------------------------------------------------------------------
-typedef int MachineOpCode;
+typedef short MachineOpCode;
typedef unsigned InstrSchedClass;
-const MachineOpCode INVALID_MACHINE_OPCODE = -1;
-
-
//---------------------------------------------------------------------------
// struct TargetInstrDescriptor:
// Predefined information about each machine instruction.
const unsigned M_BRANCH_FLAG = 1 << 1;
const unsigned M_CALL_FLAG = 1 << 2;
const unsigned M_RET_FLAG = 1 << 3;
-const unsigned M_ARITH_FLAG = 1 << 4;
const unsigned M_CC_FLAG = 1 << 6;
-const unsigned M_LOGICAL_FLAG = 1 << 6;
-const unsigned M_INT_FLAG = 1 << 7;
-const unsigned M_FLOAT_FLAG = 1 << 8;
-const unsigned M_CONDL_FLAG = 1 << 9;
const unsigned M_LOAD_FLAG = 1 << 10;
-const unsigned M_PREFETCH_FLAG = 1 << 11;
const unsigned M_STORE_FLAG = 1 << 12;
const unsigned M_DUMMY_PHI_FLAG = 1 << 13;
const unsigned M_PSEUDO_FLAG = 1 << 14; // Pseudo instruction
const char * Name; // Assembly language mnemonic for the opcode.
int numOperands; // Number of args; -1 if variable #args
int resultPos; // Position of the result; -1 if no result
- unsigned maxImmedConst; // Largest +ve constant in IMMMED field or 0.
+ unsigned maxImmedConst; // Largest +ve constant in IMMED field or 0.
bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
// smallest -ve value is -(maxImmedConst+1).
unsigned numDelaySlots; // Number of delay slots after instruction
///
class TargetInstrInfo {
const TargetInstrDescriptor* desc; // raw array to allow static init'n
- unsigned descSize; // number of entries in the desc array
+ unsigned NumOpcodes; // number of entries in the desc array
unsigned numRealOpCodes; // number of non-dummy op codes
TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
public:
- TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned descSize,
- unsigned numRealOpCodes);
+ TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
virtual ~TargetInstrInfo();
- // Invariant: All instruction sets use opcode #0 as the PHI instruction and
- // opcode #1 as the noop instruction.
- enum {
- PHI = 0, NOOP = 1
- };
+ // Invariant: All instruction sets use opcode #0 as the PHI instruction
+ enum { PHI = 0 };
- unsigned getNumRealOpCodes() const { return numRealOpCodes; }
- unsigned getNumTotalOpCodes() const { return descSize; }
+ unsigned getNumOpcodes() const { return NumOpcodes; }
/// get - Return the machine instruction descriptor that corresponds to the
/// specified instruction opcode.
///
const TargetInstrDescriptor& get(MachineOpCode opCode) const {
- assert(opCode >= 0 && opCode < (int)descSize);
+ assert((unsigned)opCode < NumOpcodes);
return desc[opCode];
}
- /// print - Print out the specified machine instruction in the appropriate
- /// target specific assembly language. If this method is not overridden, the
- /// default implementation uses the crummy machine independant printer.
- ///
- virtual void print(const MachineInstr *MI, std::ostream &O,
- const TargetMachine &TM) const;
-
const char *getName(MachineOpCode opCode) const {
return get(opCode).Name;
}
int getNumOperands(MachineOpCode opCode) const {
return get(opCode).numOperands;
}
-
- int getResultPos(MachineOpCode opCode) const {
- return get(opCode).resultPos;
- }
-
- unsigned getNumDelaySlots(MachineOpCode opCode) const {
- return get(opCode).numDelaySlots;
- }
-
+
+
InstrSchedClass getSchedClass(MachineOpCode opCode) const {
return get(opCode).schedClass;
}
-
+
+ const unsigned *getImplicitUses(MachineOpCode opCode) const {
+ return get(opCode).ImplicitUses;
+ }
+
+ const unsigned *getImplicitDefs(MachineOpCode opCode) const {
+ return get(opCode).ImplicitDefs;
+ }
+
+
//
// Query instruction class flags according to the machine-independent
// flags listed above.
//
- bool isNop(MachineOpCode opCode) const {
- return get(opCode).Flags & M_NOP_FLAG;
+ bool isReturn(MachineOpCode opCode) const {
+ return get(opCode).Flags & M_RET_FLAG;
}
- bool isBranch(MachineOpCode opCode) const {
- return get(opCode).Flags & M_BRANCH_FLAG;
+
+ bool isPseudoInstr(MachineOpCode opCode) const {
+ return get(opCode).Flags & M_PSEUDO_FLAG;
}
- bool isCall(MachineOpCode opCode) const {
- return get(opCode).Flags & M_CALL_FLAG;
+ bool isTwoAddrInstr(MachineOpCode opCode) const {
+ return get(opCode).Flags & M_2_ADDR_FLAG;
}
- bool isReturn(MachineOpCode opCode) const {
- return get(opCode).Flags & M_RET_FLAG;
+ bool isTerminatorInstr(unsigned Opcode) const {
+ return get(Opcode).Flags & M_TERMINATOR_FLAG;
+ }
+
+ //
+ // Return true if the instruction is a register to register move and
+ // leave the source and dest operands in the passed parameters.
+ //
+ virtual bool isMoveInstr(const MachineInstr& MI,
+ unsigned& sourceReg,
+ unsigned& destReg) const {
+ return false;
}
- bool isControlFlow(MachineOpCode opCode) const {
- return get(opCode).Flags & M_BRANCH_FLAG
- || get(opCode).Flags & M_CALL_FLAG
- || get(opCode).Flags & M_RET_FLAG;
+
+
+
+
+ //-------------------------------------------------------------------------
+ // Code generation support for creating individual machine instructions
+ //
+ // WARNING: These methods are Sparc specific
+ //
+ // DO NOT USE ANY OF THESE METHODS THEY ARE DEPRECATED!
+ //
+ //-------------------------------------------------------------------------
+
+ int getResultPos(MachineOpCode opCode) const {
+ return get(opCode).resultPos;
}
- bool isArith(MachineOpCode opCode) const {
- return get(opCode).Flags & M_ARITH_FLAG;
+ unsigned getNumDelaySlots(MachineOpCode opCode) const {
+ return get(opCode).numDelaySlots;
}
bool isCCInstr(MachineOpCode opCode) const {
return get(opCode).Flags & M_CC_FLAG;
}
- bool isLogical(MachineOpCode opCode) const {
- return get(opCode).Flags & M_LOGICAL_FLAG;
- }
- bool isIntInstr(MachineOpCode opCode) const {
- return get(opCode).Flags & M_INT_FLAG;
+ bool isNop(MachineOpCode opCode) const {
+ return get(opCode).Flags & M_NOP_FLAG;
}
- bool isFloatInstr(MachineOpCode opCode) const {
- return get(opCode).Flags & M_FLOAT_FLAG;
+ bool isBranch(MachineOpCode opCode) const {
+ return get(opCode).Flags & M_BRANCH_FLAG;
}
- bool isConditional(MachineOpCode opCode) const {
- return get(opCode).Flags & M_CONDL_FLAG;
+ bool isCall(MachineOpCode opCode) const {
+ return get(opCode).Flags & M_CALL_FLAG;
}
bool isLoad(MachineOpCode opCode) const {
return get(opCode).Flags & M_LOAD_FLAG;
}
- bool isPrefetch(MachineOpCode opCode) const {
- return get(opCode).Flags & M_PREFETCH_FLAG;
- }
- bool isLoadOrPrefetch(MachineOpCode opCode) const {
- return get(opCode).Flags & M_LOAD_FLAG
- || get(opCode).Flags & M_PREFETCH_FLAG;
- }
bool isStore(MachineOpCode opCode) const {
return get(opCode).Flags & M_STORE_FLAG;
}
- bool isMemoryAccess(MachineOpCode opCode) const {
- return get(opCode).Flags & M_LOAD_FLAG
- || get(opCode).Flags & M_PREFETCH_FLAG
- || get(opCode).Flags & M_STORE_FLAG;
- }
bool isDummyPhiInstr(MachineOpCode opCode) const {
return get(opCode).Flags & M_DUMMY_PHI_FLAG;
}
- bool isPseudoInstr(MachineOpCode opCode) const {
- return get(opCode).Flags & M_PSEUDO_FLAG;
- }
- bool isTwoAddrInstr(MachineOpCode opCode) const {
- return get(opCode).Flags & M_2_ADDR_FLAG;
- }
- bool isTerminatorInstr(unsigned Opcode) const {
- return get(Opcode).Flags & M_TERMINATOR_FLAG;
- }
-
// Check if an instruction can be issued before its operands are ready,
// or if a subsequent instruction that uses its result can be issued
// before the results are ready.
//
virtual bool hasOperandInterlock(MachineOpCode opCode) const {
return true;
- }
-
+ }
virtual bool hasResultInterlock(MachineOpCode opCode) const {
return true;
}
virtual bool constantFitsInImmedField(MachineOpCode opCode,
int64_t intValue) const;
- // Return the largest +ve constant that can be held in the IMMMED field
+ // Return the largest positive constant that can be held in the IMMED field
// of this machine instruction.
// isSignExtended is set to true if the value is sign-extended before use
// (this is true for all immediate fields in SPARC instructions).
return true; // safe but very conservative
}
-
- /// createNOPinstr - returns the target's implementation of NOP, which is
- /// usually a pseudo-instruction, implemented by a degenerate version of
- /// another instruction, e.g. X86: xchg ax, ax; SparcV9: sethi g0, 0
- ///
- virtual MachineInstr* createNOPinstr() const = 0;
-
- /// isNOPinstr - not having a special NOP opcode, we need to know if a given
- /// instruction is interpreted as an `official' NOP instr, i.e., there may be
- /// more than one way to `do nothing' but only one canonical way to slack off.
- ///
- virtual bool isNOPinstr(const MachineInstr &MI) const = 0;
-
- //-------------------------------------------------------------------------
- // Code generation support for creating individual machine instructions
- //
- // WARNING: These methods are Sparc specific
- //
- //-------------------------------------------------------------------------
-
// Get certain common op codes for the current target. this and all the
// Create* methods below should be moved to a machine code generation class
//
virtual MachineOpCode getNOPOpCode() const { abort(); }
+ // Get the value of an integral constant in the form that must
+ // be put into the machine register. The specified constant is interpreted
+ // as (i.e., converted if necessary to) the specified destination type. The
+ // result is always returned as an uint64_t, since the representation of
+ // int64_t and uint64_t are identical. The argument can be any known const.
+ //
+ // isValidConstant is set to true if a valid constant was found.
+ //
+ virtual uint64_t ConvertConstantToIntType(const TargetMachine &target,
+ const Value *V,
+ const Type *destType,
+ bool &isValidConstant) const {
+ abort();
+ }
+
// Create an instruction sequence to put the constant `val' into
// the virtual register `dest'. `val' may be a Constant or a
// GlobalValue, viz., the constant address of a global variable or function.
}
};
+} // End llvm namespace
+
#endif
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