#ifndef LLVM_TARGET_TARGETINSTRINFO_H
#define LLVM_TARGET_TARGETINSTRINFO_H
+#include "llvm/CodeGen/MachineBasicBlock.h"
#include "Support/DataTypes.h"
#include <vector>
#include <cassert>
return get(Opcode).Flags & M_TERMINATOR_FLAG;
}
- //
- // Return true if the instruction is a register to register move and
- // leave the source and dest operands in the passed parameters.
- //
+ /// Return true if the instruction is a register to register move
+ /// and leave the source and dest operands in the passed parameters.
virtual bool isMoveInstr(const MachineInstr& MI,
unsigned& sourceReg,
unsigned& destReg) const {
return false;
}
+ /// Insert a goto (unconditional branch) sequence to TMBB, at the
+ /// end of MBB
+ virtual void insertGoto(MachineBasicBlock& MBB,
+ MachineBasicBlock& TMBB) const {
+ assert(0 && "Target didn't implement insertGoto!");
+ }
-
+ /// Reverses the branch condition of the MachineInstr pointed by
+ /// MI. The instruction is replaced and the new MI is returned.
+ virtual MachineBasicBlock::iterator
+ reverseBranchCondition(MachineBasicBlock::iterator MI) const {
+ assert(0 && "Target didn't implement reverseBranchCondition!");
+ abort();
+ return MI;
+ }
//-------------------------------------------------------------------------
// Code generation support for creating individual machine instructions
//
//-------------------------------------------------------------------------
- int getResultPos(MachineOpCode Opcode) const {
- return get(Opcode).resultPos;
- }
unsigned getNumDelaySlots(MachineOpCode Opcode) const {
return get(Opcode).numDelaySlots;
}