//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
//
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
// This file describes the target machine instructions to the code generator.
//
//===----------------------------------------------------------------------===//
-#ifndef LLVM_TARGET_MACHINEINSTRINFO_H
-#define LLVM_TARGET_MACHINEINSTRINFO_H
+#ifndef LLVM_TARGET_TARGETINSTRINFO_H
+#define LLVM_TARGET_TARGETINSTRINFO_H
-#include "Support/DataTypes.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/Support/DataTypes.h"
#include <vector>
+#include <cassert>
+
+namespace llvm {
class MachineInstr;
class TargetMachine;
class Value;
+class Type;
class Instruction;
class Constant;
class Function;
class MachineCodeForInstruction;
+class TargetRegisterClass;
//---------------------------------------------------------------------------
// Data types used to define information about a single machine instruction
//---------------------------------------------------------------------------
-typedef int MachineOpCode;
+typedef short MachineOpCode;
typedef unsigned InstrSchedClass;
-const MachineOpCode INVALID_MACHINE_OPCODE = -1;
+//---------------------------------------------------------------------------
+// struct TargetInstrDescriptor:
+// Predefined information about each machine instruction.
+// Designed to initialized statically.
+//
+const unsigned M_NOP_FLAG = 1 << 0;
+const unsigned M_BRANCH_FLAG = 1 << 1;
+const unsigned M_CALL_FLAG = 1 << 2;
+const unsigned M_RET_FLAG = 1 << 3;
+const unsigned M_BARRIER_FLAG = 1 << 4;
+const unsigned M_DELAY_SLOT_FLAG = 1 << 5;
+const unsigned M_CC_FLAG = 1 << 6;
+const unsigned M_LOAD_FLAG = 1 << 7;
+const unsigned M_STORE_FLAG = 1 << 8;
-//---------------------------------------------------------------------------
-// struct MachineInstrDescriptor:
-// Predefined information about each machine instruction.
-// Designed to initialized statically.
-//
-// class MachineInstructionInfo
-// Interface to description of machine instructions
-//
-//---------------------------------------------------------------------------
+// M_2_ADDR_FLAG - 3-addr instructions which really work like 2-addr ones.
+const unsigned M_2_ADDR_FLAG = 1 << 9;
+
+// M_CONVERTIBLE_TO_3_ADDR - This is a M_2_ADDR_FLAG instruction which can be
+// changed into a 3-address instruction if the first two operands cannot be
+// assigned to the same register. The target must implement the
+// TargetInstrInfo::convertToThreeAddress method for this instruction.
+const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 10;
-const unsigned M_NOP_FLAG = 1 << 0;
-const unsigned M_BRANCH_FLAG = 1 << 1;
-const unsigned M_CALL_FLAG = 1 << 2;
-const unsigned M_RET_FLAG = 1 << 3;
-const unsigned M_ARITH_FLAG = 1 << 4;
-const unsigned M_CC_FLAG = 1 << 6;
-const unsigned M_LOGICAL_FLAG = 1 << 6;
-const unsigned M_INT_FLAG = 1 << 7;
-const unsigned M_FLOAT_FLAG = 1 << 8;
-const unsigned M_CONDL_FLAG = 1 << 9;
-const unsigned M_LOAD_FLAG = 1 << 10;
-const unsigned M_PREFETCH_FLAG = 1 << 11;
-const unsigned M_STORE_FLAG = 1 << 12;
-const unsigned M_DUMMY_PHI_FLAG = 1 << 13;
-const unsigned M_PSEUDO_FLAG = 1 << 14; // Pseudo instruction
-// 3-addr instructions which really work like 2-addr ones, eg. X86 add/sub
-const unsigned M_2_ADDR_FLAG = 1 << 15;
+// This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y,
+// Z), which produces the same result if Y and Z are exchanged.
+const unsigned M_COMMUTABLE = 1 << 11;
// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
// block? Typically this is things like return and branch instructions.
// Various passes use this to insert code into the bottom of a basic block, but
// before control flow occurs.
-const unsigned M_TERMINATOR_FLAG = 1 << 16;
+const unsigned M_TERMINATOR_FLAG = 1 << 12;
+
+// M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom
+// insertion support when the DAG scheduler is inserting it into a machine basic
+// block.
+const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 13;
+
+/// TargetOperandInfo - This holds information about one operand of a machine
+/// instruction, indicating the register class for register operands, etc.
+///
+class TargetOperandInfo {
+public:
+ /// RegClass - This specifies the register class of the operand if the
+ /// operand is a register. If not, this contains null.
+ const TargetRegisterClass *RegClass;
+
+ /// Currently no other information.
+};
-struct TargetInstrDescriptor {
+
+class TargetInstrDescriptor {
+public:
const char * Name; // Assembly language mnemonic for the opcode.
int numOperands; // Number of args; -1 if variable #args
int resultPos; // Position of the result; -1 if no result
- unsigned maxImmedConst; // Largest +ve constant in IMMMED field or 0.
- bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
+ unsigned maxImmedConst; // Largest +ve constant in IMMED field or 0.
+ bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
// smallest -ve value is -(maxImmedConst+1).
unsigned numDelaySlots; // Number of delay slots after instruction
unsigned latency; // Latency in machine cycles
unsigned TSFlags; // Target Specific Flag values
const unsigned *ImplicitUses; // Registers implicitly read by this instr
const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
+ const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands.
};
-typedef TargetInstrDescriptor MachineInstrDescriptor;
+//---------------------------------------------------------------------------
+///
+/// TargetInstrInfo - Interface to description of machine instructions
+///
class TargetInstrInfo {
const TargetInstrDescriptor* desc; // raw array to allow static init'n
- unsigned descSize; // number of entries in the desc array
+ unsigned NumOpcodes; // number of entries in the desc array
unsigned numRealOpCodes; // number of non-dummy op codes
-
+
TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
public:
- TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned descSize,
- unsigned numRealOpCodes);
+ TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
virtual ~TargetInstrInfo();
- // Invariant: All instruction sets use opcode #0 as the PHI instruction and
- // opcode #1 as the noop instruction.
- enum {
- PHI = 0, NOOP = 1
- };
-
- unsigned getNumRealOpCodes() const { return numRealOpCodes; }
- unsigned getNumTotalOpCodes() const { return descSize; }
-
+ // Invariant: All instruction sets use opcode #0 as the PHI instruction
+ enum { PHI = 0 };
+
+ unsigned getNumOpcodes() const { return NumOpcodes; }
+
/// get - Return the machine instruction descriptor that corresponds to the
/// specified instruction opcode.
///
- const TargetInstrDescriptor& get(MachineOpCode opCode) const {
- assert(opCode >= 0 && opCode < (int)descSize);
- return desc[opCode];
+ const TargetInstrDescriptor& get(MachineOpCode Opcode) const {
+ assert((unsigned)Opcode < NumOpcodes);
+ return desc[Opcode];
}
- /// print - Print out the specified machine instruction in the appropriate
- /// target specific assembly language. If this method is not overridden, the
- /// default implementation uses the crummy machine independant printer.
- ///
- virtual void print(const MachineInstr *MI, std::ostream &O,
- const TargetMachine &TM) const;
-
- const char *getName(MachineOpCode opCode) const {
- return get(opCode).Name;
+ const char *getName(MachineOpCode Opcode) const {
+ return get(Opcode).Name;
}
-
- int getNumOperands(MachineOpCode opCode) const {
- return get(opCode).numOperands;
+
+ int getNumOperands(MachineOpCode Opcode) const {
+ return get(Opcode).numOperands;
}
-
- int getResultPos(MachineOpCode opCode) const {
- return get(opCode).resultPos;
+
+ InstrSchedClass getSchedClass(MachineOpCode Opcode) const {
+ return get(Opcode).schedClass;
}
-
- unsigned getNumDelaySlots(MachineOpCode opCode) const {
- return get(opCode).numDelaySlots;
+
+ const unsigned *getImplicitUses(MachineOpCode Opcode) const {
+ return get(Opcode).ImplicitUses;
}
-
- InstrSchedClass getSchedClass(MachineOpCode opCode) const {
- return get(opCode).schedClass;
+
+ const unsigned *getImplicitDefs(MachineOpCode Opcode) const {
+ return get(Opcode).ImplicitDefs;
}
-
+
+
//
// Query instruction class flags according to the machine-independent
// flags listed above.
- //
- bool isNop(MachineOpCode opCode) const {
- return get(opCode).Flags & M_NOP_FLAG;
- }
- bool isBranch(MachineOpCode opCode) const {
- return get(opCode).Flags & M_BRANCH_FLAG;
- }
- bool isCall(MachineOpCode opCode) const {
- return get(opCode).Flags & M_CALL_FLAG;
- }
- bool isReturn(MachineOpCode opCode) const {
- return get(opCode).Flags & M_RET_FLAG;
- }
- bool isControlFlow(MachineOpCode opCode) const {
- return get(opCode).Flags & M_BRANCH_FLAG
- || get(opCode).Flags & M_CALL_FLAG
- || get(opCode).Flags & M_RET_FLAG;
- }
- bool isArith(MachineOpCode opCode) const {
- return get(opCode).Flags & M_ARITH_FLAG;
- }
- bool isCCInstr(MachineOpCode opCode) const {
- return get(opCode).Flags & M_CC_FLAG;
- }
- bool isLogical(MachineOpCode opCode) const {
- return get(opCode).Flags & M_LOGICAL_FLAG;
- }
- bool isIntInstr(MachineOpCode opCode) const {
- return get(opCode).Flags & M_INT_FLAG;
- }
- bool isFloatInstr(MachineOpCode opCode) const {
- return get(opCode).Flags & M_FLOAT_FLAG;
- }
- bool isConditional(MachineOpCode opCode) const {
- return get(opCode).Flags & M_CONDL_FLAG;
- }
- bool isLoad(MachineOpCode opCode) const {
- return get(opCode).Flags & M_LOAD_FLAG;
- }
- bool isPrefetch(MachineOpCode opCode) const {
- return get(opCode).Flags & M_PREFETCH_FLAG;
- }
- bool isLoadOrPrefetch(MachineOpCode opCode) const {
- return get(opCode).Flags & M_LOAD_FLAG
- || get(opCode).Flags & M_PREFETCH_FLAG;
- }
- bool isStore(MachineOpCode opCode) const {
- return get(opCode).Flags & M_STORE_FLAG;
- }
- bool isMemoryAccess(MachineOpCode opCode) const {
- return get(opCode).Flags & M_LOAD_FLAG
- || get(opCode).Flags & M_PREFETCH_FLAG
- || get(opCode).Flags & M_STORE_FLAG;
- }
- bool isDummyPhiInstr(MachineOpCode opCode) const {
- return get(opCode).Flags & M_DUMMY_PHI_FLAG;
- }
- bool isPseudoInstr(MachineOpCode opCode) const {
- return get(opCode).Flags & M_PSEUDO_FLAG;
+ //
+ bool isReturn(MachineOpCode Opcode) const {
+ return get(Opcode).Flags & M_RET_FLAG;
}
- bool isTwoAddrInstr(MachineOpCode opCode) const {
- return get(opCode).Flags & M_2_ADDR_FLAG;
+
+ bool isTwoAddrInstr(MachineOpCode Opcode) const {
+ return get(Opcode).Flags & M_2_ADDR_FLAG;
}
bool isTerminatorInstr(unsigned Opcode) const {
return get(Opcode).Flags & M_TERMINATOR_FLAG;
}
-
- // Check if an instruction can be issued before its operands are ready,
- // or if a subsequent instruction that uses its result can be issued
- // before the results are ready.
- // Default to true since most instructions on many architectures allow this.
- //
- virtual bool hasOperandInterlock(MachineOpCode opCode) const {
- return true;
- }
- virtual bool hasResultInterlock(MachineOpCode opCode) const {
- return true;
+ bool isBranch(MachineOpCode Opcode) const {
+ return get(Opcode).Flags & M_BRANCH_FLAG;
}
- //
- // Latencies for individual instructions and instruction pairs
- //
- virtual int minLatency(MachineOpCode opCode) const {
- return get(opCode).latency;
+ /// isBarrier - Returns true if the specified instruction stops control flow
+ /// from executing the instruction immediately following it. Examples include
+ /// unconditional branches and return instructions.
+ bool isBarrier(MachineOpCode Opcode) const {
+ return get(Opcode).Flags & M_BARRIER_FLAG;
}
- virtual int maxLatency(MachineOpCode opCode) const {
- return get(opCode).latency;
+ bool isCall(MachineOpCode Opcode) const {
+ return get(Opcode).Flags & M_CALL_FLAG;
}
-
- //
- // Which operand holds an immediate constant? Returns -1 if none
- //
- virtual int getImmedConstantPos(MachineOpCode opCode) const {
- return -1; // immediate position is machine specific, so say -1 == "none"
+ bool isLoad(MachineOpCode Opcode) const {
+ return get(Opcode).Flags & M_LOAD_FLAG;
+ }
+ bool isStore(MachineOpCode Opcode) const {
+ return get(Opcode).Flags & M_STORE_FLAG;
}
- // Check if the specified constant fits in the immediate field
- // of this machine instruction
- //
- virtual bool constantFitsInImmedField(MachineOpCode opCode,
- int64_t intValue) const;
-
- // Return the largest +ve constant that can be held in the IMMMED field
- // of this machine instruction.
- // isSignExtended is set to true if the value is sign-extended before use
- // (this is true for all immediate fields in SPARC instructions).
- // Return 0 if the instruction has no IMMED field.
- //
- virtual uint64_t maxImmedConstant(MachineOpCode opCode,
- bool &isSignExtended) const {
- isSignExtended = get(opCode).immedIsSignExtended;
- return get(opCode).maxImmedConst;
+ /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
+ /// custom insertion support when the DAG scheduler is inserting it into a
+ /// machine basic block.
+ bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const {
+ return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION;
}
- //-------------------------------------------------------------------------
- // Queries about representation of LLVM quantities (e.g., constants)
- //-------------------------------------------------------------------------
+ /// Return true if the instruction is a register to register move
+ /// and leave the source and dest operands in the passed parameters.
+ virtual bool isMoveInstr(const MachineInstr& MI,
+ unsigned& sourceReg,
+ unsigned& destReg) const {
+ return false;
+ }
+
+ /// convertToThreeAddress - This method must be implemented by targets that
+ /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
+ /// may be able to convert a two-address instruction into a true
+ /// three-address instruction on demand. This allows the X86 target (for
+ /// example) to convert ADD and SHL instructions into LEA instructions if they
+ /// would require register copies due to two-addressness.
+ ///
+ /// This method returns a null pointer if the transformation cannot be
+ /// performed, otherwise it returns the new instruction.
+ ///
+ virtual MachineInstr *convertToThreeAddress(MachineInstr *TA) const {
+ return 0;
+ }
- /// ConstantTypeMustBeLoaded - Test if this type of constant must be loaded
- /// from memory into a register, i.e., cannot be set bitwise in register and
- /// cannot use immediate fields of instructions. Note that this only makes
- /// sense for primitive types.
+ /// commuteInstruction - If a target has any instructions that are commutable,
+ /// but require converting to a different instruction or making non-trivial
+ /// changes to commute them, this method can overloaded to do this. The
+ /// default implementation of this method simply swaps the first two operands
+ /// of MI and returns it.
///
- virtual bool ConstantTypeMustBeLoaded(const Constant* CV) const;
-
- // Test if this constant may not fit in the immediate field of the
- // machine instructions (probably) generated for this instruction.
- //
- virtual bool ConstantMayNotFitInImmedField(const Constant* CV,
- const Instruction* I) const {
- return true; // safe but very conservative
+ /// If a target wants to make more aggressive changes, they can construct and
+ /// return a new machine instruction. If an instruction cannot commute, it
+ /// can also return null.
+ ///
+ virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
+
+ /// Insert a goto (unconditional branch) sequence to TMBB, at the
+ /// end of MBB
+ virtual void insertGoto(MachineBasicBlock& MBB,
+ MachineBasicBlock& TMBB) const {
+ assert(0 && "Target didn't implement insertGoto!");
}
+ /// Reverses the branch condition of the MachineInstr pointed by
+ /// MI. The instruction is replaced and the new MI is returned.
+ virtual MachineBasicBlock::iterator
+ reverseBranchCondition(MachineBasicBlock::iterator MI) const {
+ assert(0 && "Target didn't implement reverseBranchCondition!");
+ abort();
+ return MI;
+ }
+
+
//-------------------------------------------------------------------------
// Code generation support for creating individual machine instructions
//
// WARNING: These methods are Sparc specific
//
+ // DO NOT USE ANY OF THESE METHODS THEY ARE DEPRECATED!
+ //
//-------------------------------------------------------------------------
- // Get certain common op codes for the current target. this and all the
- // Create* methods below should be moved to a machine code generation class
- //
- virtual MachineOpCode getNOPOpCode() const { abort(); }
-
- // Create an instruction sequence to put the constant `val' into
- // the virtual register `dest'. `val' may be a Constant or a
- // GlobalValue, viz., the constant address of a global variable or function.
- // The generated instructions are returned in `mvec'.
- // Any temp. registers (TmpInstruction) created are recorded in mcfi.
- // Symbolic constants or constants that must be accessed from memory
- // are added to the constant pool via MachineFunction::get(F).
- //
- virtual void CreateCodeToLoadConst(const TargetMachine& target,
- Function* F,
- Value* val,
- Instruction* dest,
- std::vector<MachineInstr*>& mvec,
- MachineCodeForInstruction& mcfi) const {
- abort();
+ unsigned getNumDelaySlots(MachineOpCode Opcode) const {
+ return get(Opcode).numDelaySlots;
+ }
+ bool isCCInstr(MachineOpCode Opcode) const {
+ return get(Opcode).Flags & M_CC_FLAG;
+ }
+ bool isNop(MachineOpCode Opcode) const {
+ return get(Opcode).Flags & M_NOP_FLAG;
}
- // Create an instruction sequence to copy an integer value `val'
- // to a floating point value `dest' by copying to memory and back.
- // val must be an integral type. dest must be a Float or Double.
- // The generated instructions are returned in `mvec'.
- // Any temp. registers (TmpInstruction) created are recorded in mcfi.
- // Any stack space required is allocated via mcff.
- //
- virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
- Function* F,
- Value* val,
- Instruction* dest,
- std::vector<MachineInstr*>& mvec,
- MachineCodeForInstruction& MI) const {
- abort();
+ /// hasDelaySlot - Returns true if the specified instruction has a delay slot
+ /// which must be filled by the code generator.
+ bool hasDelaySlot(unsigned Opcode) const {
+ return get(Opcode).Flags & M_DELAY_SLOT_FLAG;
}
- // Similarly, create an instruction sequence to copy an FP value
- // `val' to an integer value `dest' by copying to memory and back.
- // The generated instructions are returned in `mvec'.
- // Any temp. registers (TmpInstruction) created are recorded in mcfi.
- // Any stack space required is allocated via mcff.
- //
- virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
- Function* F,
- Value* val,
- Instruction* dest,
- std::vector<MachineInstr*>& mvec,
- MachineCodeForInstruction& MI) const {
- abort();
+ virtual bool hasResultInterlock(MachineOpCode Opcode) const {
+ return true;
}
-
- // Create instruction(s) to copy src to dest, for arbitrary types
- // The generated instructions are returned in `mvec'.
- // Any temp. registers (TmpInstruction) created are recorded in mcfi.
- // Any stack space required is allocated via mcff.
- //
- virtual void CreateCopyInstructionsByType(const TargetMachine& target,
- Function* F,
- Value* src,
- Instruction* dest,
- std::vector<MachineInstr*>& mvec,
- MachineCodeForInstruction& MI) const {
- abort();
+
+ //
+ // Latencies for individual instructions and instruction pairs
+ //
+ virtual int minLatency(MachineOpCode Opcode) const {
+ return get(Opcode).latency;
}
- // Create instruction sequence to produce a sign-extended register value
- // from an arbitrary sized value (sized in bits, not bytes).
- // The generated instructions are appended to `mvec'.
- // Any temp. registers (TmpInstruction) created are recorded in mcfi.
- // Any stack space required is allocated via mcff.
- //
- virtual void CreateSignExtensionInstructions(const TargetMachine& target,
- Function* F,
- Value* srcVal,
- Value* destVal,
- unsigned numLowBits,
- std::vector<MachineInstr*>& mvec,
- MachineCodeForInstruction& MI) const {
- abort();
+ virtual int maxLatency(MachineOpCode Opcode) const {
+ return get(Opcode).latency;
}
- // Create instruction sequence to produce a zero-extended register value
- // from an arbitrary sized value (sized in bits, not bytes).
- // The generated instructions are appended to `mvec'.
- // Any temp. registers (TmpInstruction) created are recorded in mcfi.
- // Any stack space required is allocated via mcff.
- //
- virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
- Function* F,
- Value* srcVal,
- Value* destVal,
- unsigned srcSizeInBits,
- std::vector<MachineInstr*>& mvec,
- MachineCodeForInstruction& mcfi) const {
- abort();
+ //
+ // Which operand holds an immediate constant? Returns -1 if none
+ //
+ virtual int getImmedConstantPos(MachineOpCode Opcode) const {
+ return -1; // immediate position is machine specific, so say -1 == "none"
+ }
+
+ // Check if the specified constant fits in the immediate field
+ // of this machine instruction
+ //
+ virtual bool constantFitsInImmedField(MachineOpCode Opcode,
+ int64_t intValue) const;
+
+ // Return the largest positive constant that can be held in the IMMED field
+ // of this machine instruction.
+ // isSignExtended is set to true if the value is sign-extended before use
+ // (this is true for all immediate fields in SPARC instructions).
+ // Return 0 if the instruction has no IMMED field.
+ //
+ virtual uint64_t maxImmedConstant(MachineOpCode Opcode,
+ bool &isSignExtended) const {
+ isSignExtended = get(Opcode).immedIsSignExtended;
+ return get(Opcode).maxImmedConst;
}
};
-typedef TargetInstrInfo MachineInstrInfo;
+} // End llvm namespace
#endif