//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
#ifndef LLVM_TARGET_TARGETINSTRINFO_H
#define LLVM_TARGET_TARGETINSTRINFO_H
-#include "llvm/CodeGen/MachineBasicBlock.h"
-#include "llvm/Support/DataTypes.h"
-#include <vector>
-#include <cassert>
+#include "llvm/Target/TargetInstrDesc.h"
+#include "llvm/CodeGen/MachineFunction.h"
namespace llvm {
-class MachineInstr;
-class TargetMachine;
-class Value;
-class Type;
-class Instruction;
-class Constant;
-class Function;
-class MachineCodeForInstruction;
class TargetRegisterClass;
+class LiveVariables;
+class CalleeSavedInfo;
+class SDNode;
+class SelectionDAG;
-//---------------------------------------------------------------------------
-// Data types used to define information about a single machine instruction
-//---------------------------------------------------------------------------
-
-typedef short MachineOpCode;
-typedef unsigned InstrSchedClass;
-
-//---------------------------------------------------------------------------
-// struct TargetInstrDescriptor:
-// Predefined information about each machine instruction.
-// Designed to initialized statically.
-//
-
-const unsigned M_NOP_FLAG = 1 << 0;
-const unsigned M_BRANCH_FLAG = 1 << 1;
-const unsigned M_CALL_FLAG = 1 << 2;
-const unsigned M_RET_FLAG = 1 << 3;
-const unsigned M_BARRIER_FLAG = 1 << 4;
-const unsigned M_DELAY_SLOT_FLAG = 1 << 5;
-const unsigned M_CC_FLAG = 1 << 6;
-const unsigned M_LOAD_FLAG = 1 << 7;
-const unsigned M_STORE_FLAG = 1 << 8;
-
-// M_2_ADDR_FLAG - 3-addr instructions which really work like 2-addr ones.
-const unsigned M_2_ADDR_FLAG = 1 << 9;
-
-// M_CONVERTIBLE_TO_3_ADDR - This is a M_2_ADDR_FLAG instruction which can be
-// changed into a 3-address instruction if the first two operands cannot be
-// assigned to the same register. The target must implement the
-// TargetInstrInfo::convertToThreeAddress method for this instruction.
-const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 10;
-
-// This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y,
-// Z), which produces the same result if Y and Z are exchanged.
-const unsigned M_COMMUTABLE = 1 << 11;
-
-// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
-// block? Typically this is things like return and branch instructions.
-// Various passes use this to insert code into the bottom of a basic block, but
-// before control flow occurs.
-const unsigned M_TERMINATOR_FLAG = 1 << 12;
-
-// M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom
-// insertion support when the DAG scheduler is inserting it into a machine basic
-// block.
-const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 13;
-
-/// TargetOperandInfo - This holds information about one operand of a machine
-/// instruction, indicating the register class for register operands, etc.
-///
-class TargetOperandInfo {
-public:
- /// RegClass - This specifies the register class of the operand if the
- /// operand is a register. If not, this contains null.
- const TargetRegisterClass *RegClass;
-
- /// Currently no other information.
-};
-
-
-class TargetInstrDescriptor {
-public:
- const char * Name; // Assembly language mnemonic for the opcode.
- int numOperands; // Number of args; -1 if variable #args
- int resultPos; // Position of the result; -1 if no result
- unsigned maxImmedConst; // Largest +ve constant in IMMED field or 0.
- bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
- // smallest -ve value is -(maxImmedConst+1).
- unsigned numDelaySlots; // Number of delay slots after instruction
- unsigned latency; // Latency in machine cycles
- InstrSchedClass schedClass; // enum identifying instr sched class
- unsigned Flags; // flags identifying machine instr class
- unsigned TSFlags; // Target Specific Flag values
- const unsigned *ImplicitUses; // Registers implicitly read by this instr
- const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
- const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands.
-};
+template<class T> class SmallVectorImpl;
//---------------------------------------------------------------------------
/// TargetInstrInfo - Interface to description of machine instructions
///
class TargetInstrInfo {
- const TargetInstrDescriptor* desc; // raw array to allow static init'n
- unsigned NumOpcodes; // number of entries in the desc array
- unsigned numRealOpCodes; // number of non-dummy op codes
+ const TargetInstrDesc *Descriptors; // Raw array to allow static init'n
+ unsigned NumOpcodes; // Number of entries in the desc array
TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
public:
- TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
+ TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes);
virtual ~TargetInstrInfo();
// Invariant opcodes: All instruction sets have these as their low opcodes.
enum {
PHI = 0,
- INLINEASM = 1
+ INLINEASM = 1,
+ LABEL = 2,
+ DECLARE = 3,
+ EXTRACT_SUBREG = 4,
+ INSERT_SUBREG = 5,
+ IMPLICIT_DEF = 6,
+ SUBREG_TO_REG = 7
};
unsigned getNumOpcodes() const { return NumOpcodes; }
/// get - Return the machine instruction descriptor that corresponds to the
/// specified instruction opcode.
///
- const TargetInstrDescriptor& get(MachineOpCode Opcode) const {
- assert((unsigned)Opcode < NumOpcodes);
- return desc[Opcode];
- }
-
- const char *getName(MachineOpCode Opcode) const {
- return get(Opcode).Name;
- }
-
- int getNumOperands(MachineOpCode Opcode) const {
- return get(Opcode).numOperands;
- }
-
- InstrSchedClass getSchedClass(MachineOpCode Opcode) const {
- return get(Opcode).schedClass;
+ const TargetInstrDesc &get(unsigned Opcode) const {
+ assert(Opcode < NumOpcodes && "Invalid opcode!");
+ return Descriptors[Opcode];
}
- const unsigned *getImplicitUses(MachineOpCode Opcode) const {
- return get(Opcode).ImplicitUses;
+ /// isTriviallyReMaterializable - Return true if the instruction is trivially
+ /// rematerializable, meaning it has no side effects and requires no operands
+ /// that aren't always available.
+ bool isTriviallyReMaterializable(const MachineInstr *MI) const {
+ return MI->getDesc().isRematerializable() &&
+ isReallyTriviallyReMaterializable(MI);
}
- const unsigned *getImplicitDefs(MachineOpCode Opcode) const {
- return get(Opcode).ImplicitDefs;
- }
-
-
- //
- // Query instruction class flags according to the machine-independent
- // flags listed above.
- //
- bool isReturn(MachineOpCode Opcode) const {
- return get(Opcode).Flags & M_RET_FLAG;
- }
-
- bool isTwoAddrInstr(MachineOpCode Opcode) const {
- return get(Opcode).Flags & M_2_ADDR_FLAG;
- }
- bool isTerminatorInstr(unsigned Opcode) const {
- return get(Opcode).Flags & M_TERMINATOR_FLAG;
- }
-
- bool isBranch(MachineOpCode Opcode) const {
- return get(Opcode).Flags & M_BRANCH_FLAG;
- }
-
- /// isBarrier - Returns true if the specified instruction stops control flow
- /// from executing the instruction immediately following it. Examples include
- /// unconditional branches and return instructions.
- bool isBarrier(MachineOpCode Opcode) const {
- return get(Opcode).Flags & M_BARRIER_FLAG;
- }
-
- bool isCall(MachineOpCode Opcode) const {
- return get(Opcode).Flags & M_CALL_FLAG;
- }
- bool isLoad(MachineOpCode Opcode) const {
- return get(Opcode).Flags & M_LOAD_FLAG;
- }
- bool isStore(MachineOpCode Opcode) const {
- return get(Opcode).Flags & M_STORE_FLAG;
- }
-
- /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
- /// custom insertion support when the DAG scheduler is inserting it into a
- /// machine basic block.
- bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const {
- return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION;
+protected:
+ /// isReallyTriviallyReMaterializable - For instructions with opcodes for
+ /// which the M_REMATERIALIZABLE flag is set, this function tests whether the
+ /// instruction itself is actually trivially rematerializable, considering
+ /// its operands. This is used for targets that have instructions that are
+ /// only trivially rematerializable for specific uses. This predicate must
+ /// return false if the instruction has any side effects other than
+ /// producing a value, or if it requres any address registers that are not
+ /// always available.
+ virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const {
+ return true;
}
+public:
/// Return true if the instruction is a register to register move
/// and leave the source and dest operands in the passed parameters.
virtual bool isMoveInstr(const MachineInstr& MI,
return 0;
}
+ /// reMaterialize - Re-issue the specified 'original' instruction at the
+ /// specific location targeting a new destination register.
+ virtual void reMaterialize(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned DestReg,
+ const MachineInstr *Orig) const = 0;
+
+ /// isInvariantLoad - Return true if the specified instruction (which is
+ /// marked mayLoad) is loading from a location whose value is invariant across
+ /// the function. For example, loading a value from the constant pool or from
+ /// from the argument area of a function if it does not change. This should
+ /// only return true of *all* loads the instruction does are invariant (if it
+ /// does multiple loads).
+ virtual bool isInvariantLoad(MachineInstr *MI) const {
+ return false;
+ }
+
/// convertToThreeAddress - This method must be implemented by targets that
/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
- /// may be able to convert a two-address instruction into a true
- /// three-address instruction on demand. This allows the X86 target (for
+ /// may be able to convert a two-address instruction into one or more true
+ /// three-address instructions on demand. This allows the X86 target (for
/// example) to convert ADD and SHL instructions into LEA instructions if they
/// would require register copies due to two-addressness.
///
/// This method returns a null pointer if the transformation cannot be
- /// performed, otherwise it returns the new instruction.
+ /// performed, otherwise it returns the last new instruction.
///
- virtual MachineInstr *convertToThreeAddress(MachineInstr *TA) const {
+ virtual MachineInstr *
+ convertToThreeAddress(MachineFunction::iterator &MFI,
+ MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const {
return 0;
}
/// return a new machine instruction. If an instruction cannot commute, it
/// can also return null.
///
- virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
+ /// If NewMI is true, then a new machine instruction must be created.
+ ///
+ virtual MachineInstr *commuteInstruction(MachineInstr *MI,
+ bool NewMI = false) const = 0;
+
+ /// CommuteChangesDestination - Return true if commuting the specified
+ /// instruction will also changes the destination operand. Also return the
+ /// current operand index of the would be new destination register by
+ /// reference. This can happen when the commutable instruction is also a
+ /// two-address instruction.
+ virtual bool CommuteChangesDestination(MachineInstr *MI,
+ unsigned &OpIdx) const = 0;
+
+ /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
+ /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
+ /// implemented for a target). Upon success, this returns false and returns
+ /// with the following information in various cases:
+ ///
+ /// 1. If this block ends with no branches (it just falls through to its succ)
+ /// just return false, leaving TBB/FBB null.
+ /// 2. If this block ends with only an unconditional branch, it sets TBB to be
+ /// the destination block.
+ /// 3. If this block ends with an conditional branch and it falls through to
+ /// an successor block, it sets TBB to be the branch destination block and a
+ /// list of operands that evaluate the condition. These
+ /// operands can be passed to other TargetInstrInfo methods to create new
+ /// branches.
+ /// 4. If this block ends with an conditional branch and an unconditional
+ /// block, it returns the 'true' destination in TBB, the 'false' destination
+ /// in FBB, and a list of operands that evaluate the condition. These
+ /// operands can be passed to other TargetInstrInfo methods to create new
+ /// branches.
+ ///
+ /// Note that RemoveBranch and InsertBranch must be implemented to support
+ /// cases where this method returns success.
+ ///
+ virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
+ MachineBasicBlock *&FBB,
+ std::vector<MachineOperand> &Cond) const {
+ return true;
+ }
+
+ /// RemoveBranch - Remove the branching code at the end of the specific MBB.
+ /// this is only invoked in cases where AnalyzeBranch returns success. It
+ /// returns the number of instructions that were removed.
+ virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
+ assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
+ return 0;
+ }
+
+ /// InsertBranch - Insert a branch into the end of the specified
+ /// MachineBasicBlock. This operands to this method are the same as those
+ /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch
+ /// returns success and when an unconditional branch (TBB is non-null, FBB is
+ /// null, Cond is empty) needs to be inserted. It returns the number of
+ /// instructions inserted.
+ virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
+ MachineBasicBlock *FBB,
+ const std::vector<MachineOperand> &Cond) const {
+ assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
+ return 0;
+ }
+
+ /// copyRegToReg - Add a copy between a pair of registers
+ virtual void copyRegToReg(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned DestReg, unsigned SrcReg,
+ const TargetRegisterClass *DestRC,
+ const TargetRegisterClass *SrcRC) const {
+ assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
+ }
+
+ virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned SrcReg, bool isKill, int FrameIndex,
+ const TargetRegisterClass *RC) const {
+ assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
+ }
- /// Insert a goto (unconditional branch) sequence to TMBB, at the
- /// end of MBB
- virtual void insertGoto(MachineBasicBlock& MBB,
- MachineBasicBlock& TMBB) const {
- assert(0 && "Target didn't implement insertGoto!");
+ virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const {
+ assert(0 && "Target didn't implement TargetInstrInfo::storeRegToAddr!");
}
- /// Reverses the branch condition of the MachineInstr pointed by
- /// MI. The instruction is replaced and the new MI is returned.
- virtual MachineBasicBlock::iterator
- reverseBranchCondition(MachineBasicBlock::iterator MI) const {
- assert(0 && "Target didn't implement reverseBranchCondition!");
- abort();
- return MI;
+ virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned DestReg, int FrameIndex,
+ const TargetRegisterClass *RC) const {
+ assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
+ }
+
+ virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const {
+ assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromAddr!");
}
- /// insertNoop - Insert a noop into the instruction stream at the specified
- /// point.
- virtual void insertNoop(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI) const {
- assert(0 && "Target didn't implement insertNoop!");
- abort();
+ /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
+ /// saved registers and returns true if it isn't possible / profitable to do
+ /// so by issuing a series of store instructions via
+ /// storeRegToStackSlot(). Returns false otherwise.
+ virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ const std::vector<CalleeSavedInfo> &CSI) const {
+ return false;
}
- //-------------------------------------------------------------------------
- // Code generation support for creating individual machine instructions
- //
- // WARNING: These methods are Sparc specific
- //
- // DO NOT USE ANY OF THESE METHODS THEY ARE DEPRECATED!
- //
- //-------------------------------------------------------------------------
+ /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
+ /// saved registers and returns true if it isn't possible / profitable to do
+ /// so by issuing a series of load instructions via loadRegToStackSlot().
+ /// Returns false otherwise.
+ virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ const std::vector<CalleeSavedInfo> &CSI) const {
+ return false;
+ }
+
+ /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
+ /// slot into the specified machine instruction for the specified operand(s).
+ /// If this is possible, a new instruction is returned with the specified
+ /// operand folded, otherwise NULL is returned. The client is responsible for
+ /// removing the old instruction and adding the new one in the instruction
+ /// stream.
+ virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
+ MachineInstr* MI,
+ SmallVectorImpl<unsigned> &Ops,
+ int FrameIndex) const {
+ return 0;
+ }
- unsigned getNumDelaySlots(MachineOpCode Opcode) const {
- return get(Opcode).numDelaySlots;
+ /// foldMemoryOperand - Same as the previous version except it allows folding
+ /// of any load and store from / to any address, not just from a specific
+ /// stack slot.
+ virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
+ MachineInstr* MI,
+ SmallVectorImpl<unsigned> &Ops,
+ MachineInstr* LoadMI) const {
+ return 0;
}
- bool isCCInstr(MachineOpCode Opcode) const {
- return get(Opcode).Flags & M_CC_FLAG;
+
+ /// canFoldMemoryOperand - Returns true if the specified load / store is
+ /// folding is possible.
+ virtual
+ bool canFoldMemoryOperand(MachineInstr *MI,
+ SmallVectorImpl<unsigned> &Ops) const{
+ return false;
}
- bool isNop(MachineOpCode Opcode) const {
- return get(Opcode).Flags & M_NOP_FLAG;
+
+ /// unfoldMemoryOperand - Separate a single instruction which folded a load or
+ /// a store or a load and a store into two or more instruction. If this is
+ /// possible, returns true as well as the new instructions by reference.
+ virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
+ unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const{
+ return false;
}
-
- /// hasDelaySlot - Returns true if the specified instruction has a delay slot
- /// which must be filled by the code generator.
- bool hasDelaySlot(unsigned Opcode) const {
- return get(Opcode).Flags & M_DELAY_SLOT_FLAG;
+
+ virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
+ SmallVectorImpl<SDNode*> &NewNodes) const {
+ return false;
}
- virtual bool hasResultInterlock(MachineOpCode Opcode) const {
+ /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
+ /// instruction after load / store are unfolded from an instruction of the
+ /// specified opcode. It returns zero if the specified unfolding is not
+ /// possible.
+ virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
+ bool UnfoldLoad, bool UnfoldStore) const {
+ return 0;
+ }
+
+ /// BlockHasNoFallThrough - Return true if the specified block does not
+ /// fall-through into its successor block. This is primarily used when a
+ /// branch is unanalyzable. It is useful for things like unconditional
+ /// indirect branches (jump tables).
+ virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
+ return false;
+ }
+
+ /// ReverseBranchCondition - Reverses the branch condition of the specified
+ /// condition list, returning false on success and true if it cannot be
+ /// reversed.
+ virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
return true;
}
+
+ /// insertNoop - Insert a noop into the instruction stream at the specified
+ /// point.
+ virtual void insertNoop(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI) const {
+ assert(0 && "Target didn't implement insertNoop!");
+ abort();
+ }
- //
- // Latencies for individual instructions and instruction pairs
- //
- virtual int minLatency(MachineOpCode Opcode) const {
- return get(Opcode).latency;
+ /// isPredicated - Returns true if the instruction is already predicated.
+ ///
+ virtual bool isPredicated(const MachineInstr *MI) const {
+ return false;
}
- virtual int maxLatency(MachineOpCode Opcode) const {
- return get(Opcode).latency;
+ /// isUnpredicatedTerminator - Returns true if the instruction is a
+ /// terminator instruction that has not been predicated.
+ virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
+
+ /// PredicateInstruction - Convert the instruction into a predicated
+ /// instruction. It returns true if the operation was successful.
+ virtual
+ bool PredicateInstruction(MachineInstr *MI,
+ const std::vector<MachineOperand> &Pred) const = 0;
+
+ /// SubsumesPredicate - Returns true if the first specified predicate
+ /// subsumes the second, e.g. GE subsumes GT.
+ virtual
+ bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
+ const std::vector<MachineOperand> &Pred2) const {
+ return false;
}
- //
- // Which operand holds an immediate constant? Returns -1 if none
- //
- virtual int getImmedConstantPos(MachineOpCode Opcode) const {
- return -1; // immediate position is machine specific, so say -1 == "none"
+ /// DefinesPredicate - If the specified instruction defines any predicate
+ /// or condition code register(s) used for predication, returns true as well
+ /// as the definition predicate(s) by reference.
+ virtual bool DefinesPredicate(MachineInstr *MI,
+ std::vector<MachineOperand> &Pred) const {
+ return false;
}
- // Check if the specified constant fits in the immediate field
- // of this machine instruction
- //
- virtual bool constantFitsInImmedField(MachineOpCode Opcode,
- int64_t intValue) const;
+ /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
+ /// values.
+ virtual const TargetRegisterClass *getPointerRegClass() const {
+ assert(0 && "Target didn't implement getPointerRegClass!");
+ abort();
+ return 0; // Must return a value in order to compile with VS 2005
+ }
- // Return the largest positive constant that can be held in the IMMED field
- // of this machine instruction.
- // isSignExtended is set to true if the value is sign-extended before use
- // (this is true for all immediate fields in SPARC instructions).
- // Return 0 if the instruction has no IMMED field.
- //
- virtual uint64_t maxImmedConstant(MachineOpCode Opcode,
- bool &isSignExtended) const {
- isSignExtended = get(Opcode).immedIsSignExtended;
- return get(Opcode).maxImmedConst;
+ /// GetInstSize - Returns the size of the specified Instruction.
+ ///
+ virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const {
+ assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!");
+ return 0;
}
+
+ /// GetFunctionSizeInBytes - Returns the size of the specified MachineFunction.
+ ///
+ virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0;
+
+};
+
+/// TargetInstrInfoImpl - This is the default implementation of
+/// TargetInstrInfo, which just provides a couple of default implementations
+/// for various methods. This separated out because it is implemented in
+/// libcodegen, not in libtarget.
+class TargetInstrInfoImpl : public TargetInstrInfo {
+protected:
+ TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
+ : TargetInstrInfo(desc, NumOpcodes) {}
+public:
+ virtual MachineInstr *commuteInstruction(MachineInstr *MI,
+ bool NewMI = false) const;
+ virtual bool CommuteChangesDestination(MachineInstr *MI,
+ unsigned &OpIdx) const;
+ virtual bool PredicateInstruction(MachineInstr *MI,
+ const std::vector<MachineOperand> &Pred) const;
+ virtual void reMaterialize(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned DestReg,
+ const MachineInstr *Orig) const;
+ virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const;
};
} // End llvm namespace
projects / oota-llvm.git / blobdiff