class MachineInstr;
class TargetMachine;
-class Value;
-class Type;
-class Instruction;
-class Constant;
-class Function;
class MachineCodeForInstruction;
class TargetRegisterClass;
class LiveVariables;
// execution.
const unsigned M_PREDICATED = 1 << 12;
+// M_REMATERIALIZIBLE - Set if this instruction can be trivally re-materialized
+// at any time, e.g. constant generation, load from constant pool.
+const unsigned M_REMATERIALIZIBLE = 1 << 13;
+
// Machine operand flags
// M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it
/// it is set. Returns -1 if it is not set.
int getOperandConstraint(unsigned OpNum,
TOI::OperandConstraint Constraint) const {
- assert(OpNum < numOperands && "Invalid operand # of TargetInstrInfo");
- if (OpInfo[OpNum].Constraints & (1 << Constraint)) {
+ assert((OpNum < numOperands || (Flags & M_VARIABLE_OPS)) &&
+ "Invalid operand # of TargetInstrInfo");
+ if (OpNum < numOperands &&
+ (OpInfo[OpNum].Constraints & (1 << Constraint))) {
unsigned Pos = 16 + Constraint * 4;
return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
}
return -1;
}
+
+ /// findTiedToSrcOperand - Returns the operand that is tied to the specified
+ /// dest operand. Returns -1 if there isn't one.
+ int findTiedToSrcOperand(unsigned OpNum) const;
};
// Invariant opcodes: All instruction sets have these as their low opcodes.
enum {
PHI = 0,
- INLINEASM = 1
+ INLINEASM = 1,
+ LABEL = 2
};
unsigned getNumOpcodes() const { return NumOpcodes; }
bool isPredicated(MachineOpCode Opcode) const {
return get(Opcode).Flags & M_PREDICATED;
}
+ bool isReMaterializable(MachineOpCode Opcode) const {
+ return get(Opcode).Flags & M_REMATERIALIZIBLE;
+ }
bool isCommutableInstr(MachineOpCode Opcode) const {
return get(Opcode).Flags & M_COMMUTABLE;
}
return get(Opcode).getOperandConstraint(OpNum, Constraint);
}
- /// findTiedToSrcOperand - Returns the operand that is tied to the specified
- /// dest operand. Returns -1 if there isn't one.
- int findTiedToSrcOperand(MachineOpCode Opcode, unsigned OpNum) const;
-
- /// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL
- /// instruction if it has one. This is used by codegen passes that update
- /// DWARF line number info as they modify the code.
- virtual unsigned getDWARF_LABELOpcode() const {
- return 0;
- }
-
/// Return true if the instruction is a register to register move
/// and leave the source and dest operands in the passed parameters.
virtual bool isMoveInstr(const MachineInstr& MI,
virtual const TargetRegisterClass *getPointerRegClass() const {
assert(0 && "Target didn't implement getPointerRegClass!");
abort();
+ return 0; // Must return a value in order to compile with VS 2005
}
};