Support for non-landing pad exception handling.

[oota-llvm.git] / include / llvm / Target / TargetInstrInfo.h

diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h
index db3b813d70a961b06a37b0c3a232170aecbfe270..e4b37c3bf04fb7b4d5f37eb951b7684a17d4c958 100644 (file)
--- a/include/llvm/Target/TargetInstrInfo.h
+++ b/include/llvm/Target/TargetInstrInfo.h
@@ -15,6 +15,7 @@
 #define LLVM_TARGET_TARGETINSTRINFO_H
 
 #include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/Support/DataTypes.h"
 #include <vector>
 #include <cassert>
@@ -30,6 +31,7 @@ class Constant;
 class Function;
 class MachineCodeForInstruction;
 class TargetRegisterClass;
+class LiveVariables;
 
 //---------------------------------------------------------------------------
 // Data types used to define information about a single machine instruction
@@ -91,6 +93,12 @@ const unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0;
 /// operand that controls an M_PREDICATED instruction.
 const unsigned M_PREDICATE_OPERAND = 1 << 1;
 
+namespace TOI {
+  // Operand constraints: only "tied_to" for now.
+  enum OperandConstraint {
+    TIED_TO = 0  // Must be allocated the same register as.
+  };
+}
 
 /// TargetOperandInfo - This holds information about one operand of a machine
 /// instruction, indicating the register class for register operands, etc.
@@ -110,14 +118,33 @@ public:
 
 class TargetInstrDescriptor {
 public:
+  MachineOpCode   Opcode;        // The opcode.
+  unsigned short  numOperands;   // Num of args (may be more if variable_ops).
   const char *    Name;          // Assembly language mnemonic for the opcode.
-  unsigned        numOperands;   // Num of args (may be more if variable_ops).
   InstrSchedClass schedClass;    // enum  identifying instr sched class
   unsigned        Flags;         // flags identifying machine instr class
   unsigned        TSFlags;       // Target Specific Flag values
   const unsigned *ImplicitUses;  // Registers implicitly read by this instr
   const unsigned *ImplicitDefs;  // Registers implicitly defined by this instr
   const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands.
+
+  /// getOperandConstraint - Returns the value of the specific constraint if
+  /// it is set. Returns -1 if it is not set.
+  int getOperandConstraint(unsigned OpNum,
+                           TOI::OperandConstraint Constraint) const {
+    assert((OpNum < numOperands || (Flags & M_VARIABLE_OPS)) &&
+           "Invalid operand # of TargetInstrInfo");
+    if (OpNum < numOperands &&
+        (OpInfo[OpNum].Constraints & (1 << Constraint))) {
+      unsigned Pos = 16 + Constraint * 4;
+      return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
+    }
+    return -1;
+  }
+
+  /// findTiedToSrcOperand - Returns the operand that is tied to the specified
+  /// dest operand. Returns -1 if there isn't one.
+  int findTiedToSrcOperand(unsigned OpNum) const;
 };
 
 
@@ -139,7 +166,8 @@ public:
   // Invariant opcodes: All instruction sets have these as their low opcodes.
   enum { 
     PHI = 0,
-    INLINEASM = 1
+    INLINEASM = 1,
+    LABEL = 2
   };
 
   unsigned getNumOpcodes() const { return NumOpcodes; }
@@ -229,35 +257,13 @@ public:
     return get(Opcode).Flags & M_VARIABLE_OPS;
   }
 
-  // Operand constraints: only "tied_to" for now.
-  enum OperandConstraint {
-    TIED_TO = 0  // Must be allocated the same register as.
-  };
-
   /// getOperandConstraint - Returns the value of the specific constraint if
   /// it is set. Returns -1 if it is not set.
   int getOperandConstraint(MachineOpCode Opcode, unsigned OpNum,
-                           OperandConstraint Constraint) const {
-    assert(OpNum < get(Opcode).numOperands &&
-           "Invalid operand # of TargetInstrInfo");
-    if (get(Opcode).OpInfo[OpNum].Constraints & (1 << Constraint)) {
-      unsigned Pos = 16 + Constraint * 4;
-      return (int)(get(Opcode).OpInfo[OpNum].Constraints >> Pos) & 0xf;
-    }
-    return -1;
+                           TOI::OperandConstraint Constraint) const {
+    return get(Opcode).getOperandConstraint(OpNum, Constraint);
   }
 
-  /// findTiedToSrcOperand - Returns the operand that is tied to the specified
-  /// dest operand. Returns -1 if there isn't one.
-  int findTiedToSrcOperand(MachineOpCode Opcode, unsigned OpNum) const;
-
-  /// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL
-  /// instruction if it has one.  This is used by codegen passes that update
-  /// DWARF line number info as they modify the code.
-  virtual unsigned getDWARF_LABELOpcode() const {
-    return 0;
-  }
-  
   /// Return true if the instruction is a register to register move
   /// and leave the source and dest operands in the passed parameters.
   virtual bool isMoveInstr(const MachineInstr& MI,
@@ -286,15 +292,17 @@ public:
 
   /// convertToThreeAddress - This method must be implemented by targets that
   /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
-  /// may be able to convert a two-address instruction into a true
-  /// three-address instruction on demand.  This allows the X86 target (for
+  /// may be able to convert a two-address instruction into one or moretrue
+  /// three-address instructions on demand.  This allows the X86 target (for
   /// example) to convert ADD and SHL instructions into LEA instructions if they
   /// would require register copies due to two-addressness.
   ///
   /// This method returns a null pointer if the transformation cannot be
-  /// performed, otherwise it returns the new instruction.
+  /// performed, otherwise it returns the last new instruction.
   ///
-  virtual MachineInstr *convertToThreeAddress(MachineInstr *TA) const {
+  virtual MachineInstr *
+  convertToThreeAddress(MachineFunction::iterator &MFI,
+                   MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const {
     return 0;
   }