Changed CPUResource to allow access to max num users for a resource.

[oota-llvm.git] / include / llvm / Target / TargetMachine.h

diff --git a/include/llvm/Target/TargetMachine.h b/include/llvm/Target/TargetMachine.h
index b4d5daa41ccc519f780c9fadd5b54876dc55e8d9..cfefe34c56203aa44071e92800299940ce7a510d 100644 (file)
--- a/include/llvm/Target/TargetMachine.h
+++ b/include/llvm/Target/TargetMachine.h
@@ -1,4 +1,11 @@
-//===-- llvm/Target/TargetMachine.h - General Target Information -*- C++ -*-==//
+//===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===//
+// 
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// 
+//===----------------------------------------------------------------------===//
 //
 // This file describes the general parts of a Target machine.
 //
@@ -8,19 +15,22 @@
 #define LLVM_TARGET_TARGETMACHINE_H
 
 #include "llvm/Target/TargetData.h"
-#include "Support/NonCopyable.h"
+#include <cassert>
+
+namespace llvm {
 
-class MachineInstrInfo;
-class MachineInstrDescriptor;
+class TargetInstrInfo;
+class TargetInstrDescriptor;
+class TargetJITInfo;
 class TargetSchedInfo;
 class TargetRegInfo;
 class TargetFrameInfo;
-class TargetCacheInfo;
-class TargetOptInfo;
 class MachineCodeEmitter;
 class MRegisterInfo;
+class FunctionPassManager;
 class PassManager;
 class Pass;
+class IntrinsicLowering;
 
 //===----------------------------------------------------------------------===//
 ///
@@ -28,25 +38,35 @@ class Pass;
 /// the target machine.  All target-specific information should be accessible
 /// through this interface.
 /// 
-class TargetMachine : public NonCopyableV {
+class TargetMachine {
   const std::string Name;
-  const TargetData DataLayout;         // Calculates type size & alignment
+  const TargetData DataLayout;       // Calculates type size & alignment
+  IntrinsicLowering *IL;             // Specifies how to lower intrinsic calls
   
-protected:
-  TargetMachine(const std::string &name, // Can only create subclasses...
+  TargetMachine(const TargetMachine&);   // DO NOT IMPLEMENT
+  void operator=(const TargetMachine&);  // DO NOT IMPLEMENT
+protected: // Can only create subclasses...
+  TargetMachine(const std::string &name, IntrinsicLowering *IL,                
                bool LittleEndian = false,
-                unsigned char SubWordSize = 1, unsigned char IntRegSize = 8,
                unsigned char PtrSize = 8, unsigned char PtrAl = 8,
                unsigned char DoubleAl = 8, unsigned char FloatAl = 4,
                unsigned char LongAl = 8, unsigned char IntAl = 4,
-               unsigned char ShortAl = 2, unsigned char ByteAl = 1)
-    : Name(name), DataLayout(name, LittleEndian, SubWordSize, IntRegSize,
-                            PtrSize, PtrAl, DoubleAl, FloatAl, LongAl,
-                             IntAl, ShortAl, ByteAl) {}
+               unsigned char ShortAl = 2, unsigned char ByteAl = 1);
+
+  // This constructor is used for targets that support arbitrary TargetData
+  // layouts, like the C backend.  It initializes the TargetData to match that
+  // of the specified module.
+  TargetMachine(const std::string &name, IntrinsicLowering *IL,
+                const Module &M);
 public:
-  virtual ~TargetMachine() {}
+  virtual ~TargetMachine();
 
   const std::string &getName() const { return Name; }
+
+  // getIntrinsicLowering - This method returns a reference to an
+  // IntrinsicLowering instance which should be used by the code generator to
+  // lower unknown intrinsic functions to the equivalent LLVM expansion.
+  IntrinsicLowering &getIntrinsicLowering() const { return *IL; }
   
   // Interfaces to the major aspects of target machine information:
   // -- Instruction opcode and operand information
@@ -56,12 +76,10 @@ public:
   // -- Cache hierarchy information
   // -- Machine-level optimization information (peephole only)
   // 
-  virtual const MachineInstrInfo&       getInstrInfo() const = 0;
+  virtual const TargetInstrInfo&        getInstrInfo() const = 0;
   virtual const TargetSchedInfo&        getSchedInfo() const = 0;
   virtual const TargetRegInfo&          getRegInfo()   const = 0;
   virtual const TargetFrameInfo&        getFrameInfo() const = 0;
-  virtual const TargetCacheInfo&        getCacheInfo() const = 0;
-  virtual const TargetOptInfo&          getOptInfo()   const = 0;
   const TargetData &getTargetData() const { return DataLayout; }
 
   /// getRegisterInfo - If register information is available, return it.  If
@@ -70,16 +88,16 @@ public:
   ///
   virtual const MRegisterInfo*          getRegisterInfo() const { return 0; }
 
-  // Data storage information
+  /// getJITInfo - If this target supports a JIT, return information for it,
+  /// otherwise return null.
+  ///
+  virtual TargetJITInfo *getJITInfo() { return 0; }
+
+  // Data storage information.  FIXME, this should be moved out to sparc
+  // specific code.
   // 
   virtual unsigned findOptimalStorageSize(const Type* ty) const;
   
-  /// addPassesToJITCompile - Add passes to the specified pass manager to
-  /// implement a fast dynamic compiler for this target.  Return true if this is
-  /// not supported for this target.
-  ///
-  virtual bool addPassesToJITCompile(PassManager &PM) { return true; }
-
   /// addPassesToEmitAssembly - Add passes to the specified pass manager to get
   /// assembly langage code emitted.  Typically this will involve several steps
   /// of code generation.  This method should return true if assembly emission
@@ -90,15 +108,17 @@ public:
   }
 
   /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
-  /// get machine code emitted.  This uses a MAchineCodeEmitter object to handle
+  /// get machine code emitted.  This uses a MachineCodeEmitter object to handle
   /// actually outputting the machine code and resolving things like the address
   /// of functions.  This method should returns true if machine code emission is
   /// not supported.
   ///
-  virtual bool addPassesToEmitMachineCode(PassManager &PM,
+  virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM,
                                           MachineCodeEmitter &MCE) {
     return true;
   }
 };
 
+} // End llvm namespace
+
 #endif