The TargetData is not used for the isPowerOfTwo determination. It has never

[oota-llvm.git] / include / llvm / Target / TargetOpcodes.h

diff --git a/include/llvm/Target/TargetOpcodes.h b/include/llvm/Target/TargetOpcodes.h
index 55e93eccc3cbc3018f9ff59ded3f314027eafe66..516e0706b8977b8faeeea27cbe52e4a9d187c345 100644 (file)
--- a/include/llvm/Target/TargetOpcodes.h
+++ b/include/llvm/Target/TargetOpcodes.h
@@ -25,7 +25,7 @@ namespace TargetOpcode {
   enum {
     PHI = 0,
     INLINEASM = 1,
-    DBG_LABEL = 2,
+    PROLOG_LABEL = 2,
     EH_LABEL = 3,
     GC_LABEL = 4,
 
@@ -62,8 +62,7 @@ namespace TargetOpcode {
     /// used between instruction selection and MachineInstr creation, before
     /// virtual registers have been created for all the instructions, and it's
     /// only needed in cases where the register classes implied by the
-    /// instructions are insufficient. The actual MachineInstrs to perform
-    /// the copy are emitted with the TargetInstrInfo::copyRegToReg hook.
+    /// instructions are insufficient. It is emitted as a COPY MachineInstr.
     COPY_TO_REGCLASS = 10,
 
     /// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic
@@ -72,10 +71,27 @@ namespace TargetOpcode {
     /// REG_SEQUENCE - This variadic instruction is used to form a register that
     /// represent a consecutive sequence of sub-registers. It's used as register
     /// coalescing / allocation aid and must be eliminated before code emission.
+    // In SDNode form, the first operand encodes the register class created by
+    // the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index
+    // pair.  Once it has been lowered to a MachineInstr, the regclass operand
+    // is no longer present.
     /// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5
     /// After register coalescing references of v1024 should be replace with
     /// v1027:3, v1025 with v1027:4, etc.
-    REG_SEQUENCE = 12
+    REG_SEQUENCE = 12,
+
+    /// COPY - Target-independent register copy. This instruction can also be
+    /// used to copy between subregisters of virtual registers.
+    COPY = 13,
+
+    /// BUNDLE - This instruction represents an instruction bundle. Instructions
+    /// which immediately follow a BUNDLE instruction which are marked with
+    /// 'InsideBundle' flag are inside the bundle.
+    BUNDLE = 14,
+
+    /// Lifetime markers.
+    LIFETIME_START = 15,
+    LIFETIME_END = 16
   };
 } // end namespace TargetOpcode
 } // end namespace llvm