Doxygenate comments.

[oota-llvm.git] / include / llvm / Target / TargetRegisterInfo.h

diff --git a/include/llvm/Target/TargetRegisterInfo.h b/include/llvm/Target/TargetRegisterInfo.h
index 858b0645383ef6b5ecdd4f491c58661688d1105c..105baef2bcd1ab9f6d8dbae02916bd2c540fcfec 100644 (file)
--- a/include/llvm/Target/TargetRegisterInfo.h
+++ b/include/llvm/Target/TargetRegisterInfo.h
@@ -21,7 +21,6 @@
 #include "llvm/CodeGen/ValueTypes.h"
 #include <cassert>
 #include <functional>
-#include <set>
 
 namespace llvm {
 
@@ -32,7 +31,6 @@ class MachineMove;
 class RegScavenger;
 class SDNode;
 class SelectionDAG;
-class TargetRegisterClass;
 class Type;
 
 /// TargetRegisterDesc - This record contains all of the information known about
@@ -177,36 +175,6 @@ public:
     return I;
   }
   
-  /// hasSubRegClass - return true if the specified TargetRegisterClass is a
-  /// class of a sub-register class for this TargetRegisterClass.
-  bool hasSubRegClass(const TargetRegisterClass *cs) const {
-    for (int i = 0; SubRegClasses[i] != NULL; ++i) 
-      if (SubRegClasses[i] == cs)
-        return true;
-    return false;
-  }
-
-  /// hasClassForSubReg - return true if the specified TargetRegisterClass is a
-  /// class of a sub-register class for this TargetRegisterClass.
-  bool hasClassForSubReg(unsigned SubReg) const {
-    --SubReg;
-    for (unsigned i = 0; SubRegClasses[i] != NULL; ++i) 
-      if (i == SubReg)
-        return true;
-    return false;
-  }
-
-  /// getClassForSubReg - return theTargetRegisterClass for the sub-register
-  /// at idx for this TargetRegisterClass.
-  sc_iterator getClassForSubReg(unsigned SubReg) const {
-    --SubReg;
-    for (unsigned i = 0; SubRegClasses[i] != NULL; ++i) 
-      if (i == SubReg)
-        return &SubRegClasses[i];
-    assert(0 && "Invalid subregister index for register class");
-    return NULL;
-  }
-  
   /// subregclasses_begin / subregclasses_end - Loop over all of
   /// the subregister classes of this register class.
   sc_iterator subregclasses_begin() const {
@@ -274,6 +242,9 @@ public:
 /// descriptor.
 ///
 class TargetRegisterInfo {
+protected:
+  const unsigned* SubregHash;
+  const unsigned SubregHashSize;
 public:
   typedef const TargetRegisterClass * const * regclass_iterator;
 private:
@@ -283,13 +254,14 @@ private:
   regclass_iterator RegClassBegin, RegClassEnd;   // List of regclasses
 
   int CallFrameSetupOpcode, CallFrameDestroyOpcode;
-  std::set<std::pair<unsigned, unsigned> > Subregs;
 protected:
   TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
                      regclass_iterator RegClassBegin,
                      regclass_iterator RegClassEnd,
                      int CallFrameSetupOpcode = -1,
-                     int CallFrameDestroyOpcode = -1);
+                     int CallFrameDestroyOpcode = -1,
+                     const unsigned* subregs = 0,
+                     const unsigned subregsize = 0);
   virtual ~TargetRegisterInfo();
 public:
 
@@ -410,7 +382,19 @@ public:
   /// isSubRegister - Returns true if regB is a sub-register of regA.
   ///
   bool isSubRegister(unsigned regA, unsigned regB) const {
-    return Subregs.count(std::make_pair(regA, regB));
+    // SubregHash is a simple quadratically probed hash table.
+    size_t index = (regA + regB * 37) & (SubregHashSize-1);
+    unsigned ProbeAmt = 2;
+    while (SubregHash[index*2] != 0 &&
+           SubregHash[index*2+1] != 0) {
+      if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB)
+        return true;
+      
+      index = (index + ProbeAmt) & (SubregHashSize-1);
+      ProbeAmt += 2;
+    }
+    
+    return false;
   }
 
   /// isSuperRegister - Returns true if regB is a super-register of regA.
@@ -441,7 +425,8 @@ public:
   virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
 
   /// getSubReg - Returns the physical register number of sub-register "Index"
-  /// for physical register RegNo.
+  /// for physical register RegNo. Return zero if the sub-register does not
+  /// exist.
   virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
 
   //===--------------------------------------------------------------------===//
@@ -561,16 +546,12 @@ public:
   /// eliminated by this method.  This method may modify or replace the
   /// specified instruction, as long as it keeps the iterator pointing the the
   /// finished product. SPAdj is the SP adjustment due to call frame setup
-  /// instruction. The return value is the number of instructions added to
-  /// (negative if removed from) the basic block.
-  ///
+  /// instruction.
   virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
                                    int SPAdj, RegScavenger *RS=NULL) const = 0;
 
   /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
-  /// the function. The return value is the number of instructions
-  /// added to (negative if removed from) the basic block (entry for prologue).
-  ///
+  /// the function.
   virtual void emitPrologue(MachineFunction &MF) const = 0;
   virtual void emitEpilogue(MachineFunction &MF,
                             MachineBasicBlock &MBB) const = 0;
@@ -581,7 +562,7 @@ public:
   /// getDwarfRegNum - Map a target register to an equivalent dwarf register
   /// number.  Returns -1 if there is no equivalent value.  The second
   /// parameter allows targets to use different numberings for EH info and
-  /// deubgging info.
+  /// debugging info.
   virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
 
   /// getFrameRegister - This method should return the register used as a base