return I;
}
- /// hasSubRegClass - return true if the specified TargetRegisterClass is a
- /// class of a sub-register class for this TargetRegisterClass.
- bool hasSubRegClass(const TargetRegisterClass *cs) const {
- for (int i = 0; SubRegClasses[i] != NULL; ++i)
- if (SubRegClasses[i] == cs)
- return true;
- return false;
- }
-
- /// hasClassForSubReg - return true if the specified TargetRegisterClass is a
- /// class of a sub-register class for this TargetRegisterClass.
- bool hasClassForSubReg(unsigned SubReg) const {
- --SubReg;
- for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
- if (i == SubReg)
- return true;
- return false;
- }
-
- /// getClassForSubReg - return theTargetRegisterClass for the sub-register
- /// at idx for this TargetRegisterClass.
- sc_iterator getClassForSubReg(unsigned SubReg) const {
- --SubReg;
- for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
- if (i == SubReg)
- return &SubRegClasses[i];
- assert(0 && "Invalid subregister index for register class");
- return NULL;
- }
-
/// subregclasses_begin / subregclasses_end - Loop over all of
/// the subregister classes of this register class.
sc_iterator subregclasses_begin() const {
///
class TargetRegisterInfo {
protected:
- unsigned* SubregHash;
- unsigned SubregHashSize;
+ const unsigned* SubregHash;
+ const unsigned SubregHashSize;
public:
typedef const TargetRegisterClass * const * regclass_iterator;
private:
regclass_iterator RegClassBegin,
regclass_iterator RegClassEnd,
int CallFrameSetupOpcode = -1,
- int CallFrameDestroyOpcode = -1);
+ int CallFrameDestroyOpcode = -1,
+ const unsigned* subregs = 0,
+ const unsigned subregsize = 0);
virtual ~TargetRegisterInfo();
public:
virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
/// getSubReg - Returns the physical register number of sub-register "Index"
- /// for physical register RegNo.
+ /// for physical register RegNo. Return zero if the sub-register does not
+ /// exist.
virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
//===--------------------------------------------------------------------===//