Re-enables the new vector select in the bitcode reader, by modifying the

[oota-llvm.git] / include / llvm / Target / TargetRegisterInfo.h

diff --git a/include/llvm/Target/TargetRegisterInfo.h b/include/llvm/Target/TargetRegisterInfo.h
index b385559178337bf12d79a72efb5498ea5ee8f87f..c7cc31feb91ae75726201f06f9691e9bf94bc90e 100644 (file)
--- a/include/llvm/Target/TargetRegisterInfo.h
+++ b/include/llvm/Target/TargetRegisterInfo.h
@@ -177,36 +177,6 @@ public:
     return I;
   }
   
-  /// hasSubRegClass - return true if the specified TargetRegisterClass is a
-  /// class of a sub-register class for this TargetRegisterClass.
-  bool hasSubRegClass(const TargetRegisterClass *cs) const {
-    for (int i = 0; SubRegClasses[i] != NULL; ++i) 
-      if (SubRegClasses[i] == cs)
-        return true;
-    return false;
-  }
-
-  /// hasClassForSubReg - return true if the specified TargetRegisterClass is a
-  /// class of a sub-register class for this TargetRegisterClass.
-  bool hasClassForSubReg(unsigned SubReg) const {
-    --SubReg;
-    for (unsigned i = 0; SubRegClasses[i] != NULL; ++i) 
-      if (i == SubReg)
-        return true;
-    return false;
-  }
-
-  /// getClassForSubReg - return theTargetRegisterClass for the sub-register
-  /// at idx for this TargetRegisterClass.
-  sc_iterator getClassForSubReg(unsigned SubReg) const {
-    --SubReg;
-    for (unsigned i = 0; SubRegClasses[i] != NULL; ++i) 
-      if (i == SubReg)
-        return &SubRegClasses[i];
-    assert(0 && "Invalid subregister index for register class");
-    return NULL;
-  }
-  
   /// subregclasses_begin / subregclasses_end - Loop over all of
   /// the subregister classes of this register class.
   sc_iterator subregclasses_begin() const {
@@ -275,8 +245,8 @@ public:
 ///
 class TargetRegisterInfo {
 protected:
-  unsigned* SubregHash;
-  unsigned SubregHashSize;
+  const unsigned* SubregHash;
+  const unsigned SubregHashSize;
 public:
   typedef const TargetRegisterClass * const * regclass_iterator;
 private:
@@ -291,7 +261,9 @@ protected:
                      regclass_iterator RegClassBegin,
                      regclass_iterator RegClassEnd,
                      int CallFrameSetupOpcode = -1,
-                     int CallFrameDestroyOpcode = -1);
+                     int CallFrameDestroyOpcode = -1,
+                     const unsigned* subregs = 0,
+                     const unsigned subregsize = 0);
   virtual ~TargetRegisterInfo();
 public:
 
@@ -413,14 +385,14 @@ public:
   ///
   bool isSubRegister(unsigned regA, unsigned regB) const {
     // SubregHash is a simple quadratically probed hash table.
-    size_t index = (regA + regB * 37) % SubregHashSize;
+    size_t index = (regA + regB * 37) & (SubregHashSize-1);
     unsigned ProbeAmt = 2;
     while (SubregHash[index*2] != 0 &&
            SubregHash[index*2+1] != 0) {
       if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB)
         return true;
       
-      index = (index + ProbeAmt) % SubregHashSize;
+      index = (index + ProbeAmt) & (SubregHashSize-1);
       ProbeAmt += 2;
     }
     
@@ -455,7 +427,8 @@ public:
   virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
 
   /// getSubReg - Returns the physical register number of sub-register "Index"
-  /// for physical register RegNo.
+  /// for physical register RegNo. Return zero if the sub-register does not
+  /// exist.
   virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
 
   //===--------------------------------------------------------------------===//