#include "llvm/CodeGen/ValueTypes.h"
#include <cassert>
#include <functional>
+#include <set>
namespace llvm {
/// Registers that this does not apply to simply should set this to null.
/// The SubRegs field is a zero terminated array of registers that are
/// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX.
-/// The ImmsubRegs field is a subset of SubRegs. It includes only the immediate
-/// sub-registers. e.g. EAX has only one immediate sub-register of AX, not AH,
-/// AL which are immediate sub-registers of AX. The SuperRegs field is a zero
-/// terminated array of registers that are super-registers of the specific
-/// register, e.g. RAX, EAX, are super-registers of AX.
+/// The SuperRegs field is a zero terminated array of registers that are
+/// super-registers of the specific register, e.g. RAX, EAX, are super-registers
+/// of AX.
///
struct TargetRegisterDesc {
const char *AsmName; // Assembly language name for the register
const char *Name; // Printable name for the reg (for debugging)
const unsigned *AliasSet; // Register Alias Set, described above
const unsigned *SubRegs; // Sub-register set, described above
- const unsigned *ImmSubRegs; // Immediate sub-register set, described above
const unsigned *SuperRegs; // Super-register set, described above
};
typedef const unsigned* iterator;
typedef const unsigned* const_iterator;
- typedef const MVT::ValueType* vt_iterator;
+ typedef const MVT* vt_iterator;
typedef const TargetRegisterClass* const * sc_iterator;
private:
unsigned ID;
const iterator RegsBegin, RegsEnd;
public:
TargetRegisterClass(unsigned id,
- const MVT::ValueType *vts,
+ const MVT *vts,
const TargetRegisterClass * const *subcs,
const TargetRegisterClass * const *supcs,
const TargetRegisterClass * const *subregcs,
/// getNumRegs - Return the number of registers in this class.
///
- unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
+ unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); }
/// getRegister - Return the specified register in the class.
///
/// hasType - return true if this TargetRegisterClass has the ValueType vt.
///
- bool hasType(MVT::ValueType vt) const {
+ bool hasType(MVT vt) const {
for(int i = 0; VTs[i] != MVT::Other; ++i)
if (VTs[i] == vt)
return true;
return I;
}
- /// hasSubRegClass - return true if the specified TargetRegisterClass is a
- /// class of a sub-register class for this TargetRegisterClass.
- bool hasSubRegClass(const TargetRegisterClass *cs) const {
- for (int i = 0; SubRegClasses[i] != NULL; ++i)
- if (SubRegClasses[i] == cs)
- return true;
- return false;
- }
-
- /// hasClassForSubReg - return true if the specified TargetRegisterClass is a
- /// class of a sub-register class for this TargetRegisterClass.
- bool hasClassForSubReg(unsigned SubReg) const {
- --SubReg;
- for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
- if (i == SubReg)
- return true;
- return false;
- }
-
- /// getClassForSubReg - return theTargetRegisterClass for the sub-register
- /// at idx for this TargetRegisterClass.
- sc_iterator getClassForSubReg(unsigned SubReg) const {
- --SubReg;
- for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
- if (i == SubReg)
- return &SubRegClasses[i];
- assert(0 && "Invalid subregister index for register class");
- return NULL;
- }
-
/// subregclasses_begin / subregclasses_end - Loop over all of
/// the subregister classes of this register class.
sc_iterator subregclasses_begin() const {
/// descriptor.
///
class TargetRegisterInfo {
+protected:
+ const unsigned* SubregHash;
+ const unsigned SubregHashSize;
public:
typedef const TargetRegisterClass * const * regclass_iterator;
private:
regclass_iterator RegClassBegin,
regclass_iterator RegClassEnd,
int CallFrameSetupOpcode = -1,
- int CallFrameDestroyOpcode = -1);
+ int CallFrameDestroyOpcode = -1,
+ const unsigned* subregs = 0,
+ const unsigned subregsize = 0);
virtual ~TargetRegisterInfo();
public:
}
/// getPhysicalRegisterRegClass - Returns the Register Class of a physical
- /// register of the given type.
- const TargetRegisterClass *getPhysicalRegisterRegClass(MVT::ValueType VT,
- unsigned Reg) const;
+ /// register of the given type. If type is MVT::Other, then just return any
+ /// register class the register belongs to.
+ const TargetRegisterClass *getPhysicalRegisterRegClass(unsigned Reg,
+ MVT VT = MVT::Other) const;
/// getAllocatableSet - Returns a bitset indexed by register number
/// indicating if a register is allocatable or not. If a register class is
return get(RegNo).AliasSet;
}
- /// getSubRegisters - Return the set of registers that are sub-registers of
+ /// getSubRegisters - Return the list of registers that are sub-registers of
/// the specified register, or a null list of there are none. The list
- /// returned is zero terminated.
+ /// returned is zero terminated and sorted according to super-sub register
+ /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
///
const unsigned *getSubRegisters(unsigned RegNo) const {
return get(RegNo).SubRegs;
}
- /// getImmediateSubRegisters - Return the set of registers that are immediate
- /// sub-registers of the specified register, or a null list of there are none.
- /// The list returned is zero terminated.
- ///
- const unsigned *getImmediateSubRegisters(unsigned RegNo) const {
- return get(RegNo).ImmSubRegs;
- }
-
- /// getSuperRegisters - Return the set of registers that are super-registers
+ /// getSuperRegisters - Return the list of registers that are super-registers
/// of the specified register, or a null list of there are none. The list
- /// returned is zero terminated.
+ /// returned is zero terminated and sorted according to super-sub register
+ /// relations. e.g. X86::AL's super-register list is RAX, EAX, AX.
///
const unsigned *getSuperRegisters(unsigned RegNo) const {
return get(RegNo).SuperRegs;
/// isSubRegister - Returns true if regB is a sub-register of regA.
///
bool isSubRegister(unsigned regA, unsigned regB) const {
- for (const unsigned *SR = getSubRegisters(regA); *SR; ++SR)
- if (*SR == regB) return true;
+ // SubregHash is a simple quadratically probed hash table.
+ size_t index = (regA + regB * 37) & (SubregHashSize-1);
+ unsigned ProbeAmt = 2;
+ while (SubregHash[index*2] != 0 &&
+ SubregHash[index*2+1] != 0) {
+ if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB)
+ return true;
+
+ index = (index + ProbeAmt) & (SubregHashSize-1);
+ ProbeAmt += 2;
+ }
+
return false;
}
virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
/// getSubReg - Returns the physical register number of sub-register "Index"
- /// for physical register RegNo.
+ /// for physical register RegNo. Return zero if the sub-register does not
+ /// exist.
virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
//===--------------------------------------------------------------------===//
regclass_iterator regclass_end() const { return RegClassEnd; }
unsigned getNumRegClasses() const {
- return regclass_end()-regclass_begin();
+ return (unsigned)(regclass_end()-regclass_begin());
}
/// getRegClass - Returns the register class associated with the enumeration
return NULL;
}
- /// reMaterialize - Re-issue the specified 'original' instruction at the
- /// specific location targeting a new destination register.
- virtual void reMaterialize(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned DestReg,
- const MachineInstr *Orig) const = 0;
-
/// targetHandlesStackFrameRounding - Returns true if the target is
/// responsible for rounding up the stack frame (probably at emitPrologue
/// time).
return !hasFP(MF);
}
+ // needsStackRealignment - true if storage within the function requires the
+ // stack pointer to be aligned more than the normal calling convention calls
+ // for.
+ virtual bool needsStackRealignment(const MachineFunction &MF) const {
+ return false;
+ }
+
/// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
/// frame setup/destroy instructions if they exist (-1 otherwise). Some
/// targets use pseudo instructions in order to abstract away the difference
projects / oota-llvm.git / blobdiff