//
// This file describes the target machine to the instruction scheduler.
//
+// NOTE: This file is currently sparc V9 specific.
+//
//===----------------------------------------------------------------------===//
#ifndef LLVM_TARGET_TARGETSCHEDINFO_H
#define LLVM_TARGET_TARGETSCHEDINFO_H
#include "llvm/Target/TargetInstrInfo.h"
-#include "Support/hash_map"
+#include "llvm/ADT/hash_map"
#include <string>
namespace llvm {
typedef long long cycles_t;
static const cycles_t HUGE_LATENCY = ~((long long) 1 << (sizeof(cycles_t)-2));
static const cycles_t INVALID_LATENCY = -HUGE_LATENCY;
-static const unsigned MAX_OPCODE_SIZE = 16;
-
-class OpCodePair {
-public:
- long val; // make long by concatenating two opcodes
- OpCodePair(MachineOpCode op1, MachineOpCode op2)
- : val((op1 < 0 || op2 < 0)?
- -1 : (long)((((unsigned) op1) << MAX_OPCODE_SIZE) | (unsigned) op2)) {}
- bool operator==(const OpCodePair& op) const {
- return val == op.val;
- }
-private:
- OpCodePair(); // disable for now
-};
-
-} // End llvm namespace
-
-namespace HASH_NAMESPACE {
- template <> struct hash<llvm::OpCodePair> {
- size_t operator()(const llvm::OpCodePair& pair) const {
- return hash<long>()(pair.val);
- }
- };
-} // End HASH_NAMESPACE (a macro) namespace
-
-namespace llvm {
//---------------------------------------------------------------------------
// class MachineResource
typedef unsigned resourceId_t;
-struct MachineResource {
+struct CPUResource {
const std::string rname;
resourceId_t rid;
+ int maxNumUsers; // MAXINT if no restriction
- MachineResource(const std::string &resourceName)
- : rname(resourceName), rid(nextId++) {}
-
+ CPUResource(const std::string& resourceName, int maxUsers);
+ static CPUResource* getCPUResource(resourceId_t id);
private:
static resourceId_t nextId;
- MachineResource(); // disable
-};
-
-
-struct CPUResource : public MachineResource {
- int maxNumUsers; // MAXINT if no restriction
-
- CPUResource(const std::string& rname, int maxUsers)
- : MachineResource(rname), maxNumUsers(maxUsers) {}
};
/// TargetSchedInfo - Common interface to machine information for
/// instruction scheduling
///
-struct TargetSchedInfo {
+class TargetSchedInfo {
+public:
const TargetMachine& target;
unsigned maxNumIssueTotal;
int longestIssueConflict;
- int branchMispredictPenalty; // 4 for SPARC IIi
- int branchTargetUnknownPenalty; // 2 for SPARC IIi
- int l1DCacheMissPenalty; // 7 or 9 for SPARC IIi
- int l1ICacheMissPenalty; // ? for SPARC IIi
-
- bool inOrderLoads; // true for SPARC IIi
- bool inOrderIssue; // true for SPARC IIi
- bool inOrderExec; // false for most architectures
- bool inOrderRetire; // true for most architectures
-
protected:
inline const InstrRUsage& getInstrRUsage(MachineOpCode opCode) const {
assert(opCode >= 0 && opCode < (int) instrRUsages.size());
conflictLists; // indexed by [opcode]
-
- friend class ModuloSchedGraph;
- friend class ModuloScheduling;
+ friend class ModuloSchedulingPass;
+ friend class MSSchedule;
};