Eliminate the distinction between "real" and "unreal" instructions

[oota-llvm.git] / include / llvm / Target / TargetSchedInfo.h

diff --git a/include/llvm/Target/TargetSchedInfo.h b/include/llvm/Target/TargetSchedInfo.h
index 00d4b188dce5ed48fefb9039fad224bf4b204039..ae97d109e3317d01c90f184669d302f541685d8a 100644 (file)
--- a/include/llvm/Target/TargetSchedInfo.h
+++ b/include/llvm/Target/TargetSchedInfo.h
@@ -1,14 +1,24 @@
-//===- Target/MachineSchedInfo.h - Target Instruction Sched Info -*- C++ -*-==//
+//===- Target/TargetSchedInfo.h - Target Instruction Sched Info -*- C++ -*-===//
+// 
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// 
+//===----------------------------------------------------------------------===//
 //
 // This file describes the target machine to the instruction scheduler.
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_TARGET_MACHINESCHEDINFO_H
-#define LLVM_TARGET_MACHINESCHEDINFO_H
+#ifndef LLVM_TARGET_TARGETSCHEDINFO_H
+#define LLVM_TARGET_TARGETSCHEDINFO_H
+
+#include "llvm/Target/TargetInstrInfo.h"
+#include "Support/hash_map"
+#include <string>
 
-#include "llvm/Target/MachineInstrInfo.h"
-#include <Support/hash_map>
+namespace llvm {
 
 typedef long long cycles_t; 
 static const cycles_t HUGE_LATENCY = ~((long long) 1 << (sizeof(cycles_t)-2));
@@ -28,13 +38,17 @@ private:
   OpCodePair();                        // disable for now
 };
 
+} // End llvm namespace
+
 namespace HASH_NAMESPACE {
-  template <> struct hash<OpCodePair> {
-    size_t operator()(const OpCodePair& pair) const {
+  template <> struct hash<llvm::OpCodePair> {
+    size_t operator()(const llvm::OpCodePair& pair) const {
       return hash<long>()(pair.val);
     }
   };
-}
+} // End HASH_NAMESPACE (a macro) namespace
+
+namespace llvm {
 
 //---------------------------------------------------------------------------
 // class MachineResource 
@@ -163,19 +177,15 @@ private:
     feasibleSlots.resize(maxNumSlots);
   }
   
-  friend class MachineSchedInfo;       // give access to these functions
+  friend class TargetSchedInfo;        // give access to these functions
 };
 
 
 //---------------------------------------------------------------------------
-// class MachineSchedInfo
-//
-// Purpose:
-//   Common interface to machine information for instruction scheduling
-//---------------------------------------------------------------------------
-
-class MachineSchedInfo : public NonCopyableV {
-public:
+/// TargetSchedInfo - Common interface to machine information for 
+/// instruction scheduling
+///
+struct TargetSchedInfo {
   const TargetMachine& target;
   
   unsigned maxNumIssueTotal;
@@ -196,23 +206,25 @@ protected:
     assert(opCode >= 0 && opCode < (int) instrRUsages.size());
     return instrRUsages[opCode];
   }
-  inline const InstrClassRUsage&
-                       getClassRUsage(const InstrSchedClass& sc) const {
-    assert(sc >= 0 && sc < numSchedClasses);
+  const InstrClassRUsage& getClassRUsage(const InstrSchedClass& sc) const {
+    assert(sc < numSchedClasses);
     return classRUsages[sc];
   }
-  
+
+private:
+  TargetSchedInfo(const TargetSchedInfo &);  // DO NOT IMPLEMENT
+  void operator=(const TargetSchedInfo &);  // DO NOT IMPLEMENT
 public:
-  /*ctor*/        MachineSchedInfo     (const TargetMachine& tgt,
+  /*ctor*/        TargetSchedInfo      (const TargetMachine& tgt,
                                          int                  _numSchedClasses,
                                         const InstrClassRUsage* _classRUsages,
                                         const InstrRUsageDelta* _usageDeltas,
                                         const InstrIssueDelta*  _issueDeltas,
                                         unsigned _numUsageDeltas,
                                         unsigned _numIssueDeltas);
-  /*dtor*/ virtual ~MachineSchedInfo   () {}
+  /*dtor*/ virtual ~TargetSchedInfo() {}
   
-  inline const MachineInstrInfo& getInstrInfo() const {
+  inline const TargetInstrInfo& getInstrInfo() const {
     return *mii;
   }
   
@@ -225,7 +237,7 @@ public:
   }
   
   inline  unsigned getMaxIssueForClass(const InstrSchedClass& sc) const {
-    assert(sc >= 0 && sc < numSchedClasses);
+    assert(sc < numSchedClasses);
     return classRUsages[sc].maxNumIssue;
   }
 
@@ -242,21 +254,20 @@ public:
   inline int   getLongestIssueConflict () const {
     return longestIssueConflict;
   }
-  
+
   inline  int  getMinIssueGap          (MachineOpCode fromOp,
                                         MachineOpCode toOp)   const {
-    hash_map<OpCodePair,int>::const_iterator
-      I = issueGaps.find(OpCodePair(fromOp, toOp));
-    return (I == issueGaps.end())? 0 : (*I).second;
+    assert(fromOp < (int) issueGaps.size());
+    const std::vector<int>& toGaps = issueGaps[fromOp];
+    return (toOp < (int) toGaps.size())? toGaps[toOp] : 0;
   }
-  
-  inline const std::vector<MachineOpCode>*
+
+  inline const std::vector<MachineOpCode>&
                getConflictList(MachineOpCode opCode) const {
-    hash_map<MachineOpCode, std::vector<MachineOpCode> >::const_iterator
-      I = conflictLists.find(opCode);
-    return (I == conflictLists.end())? NULL : & (*I).second;
+    assert(opCode < (int) conflictLists.size());
+    return conflictLists[opCode];
   }
-  
+
   inline  bool isSingleIssue           (MachineOpCode opCode) const {
     return getInstrRUsage(opCode).isSingleIssue;
   }
@@ -269,6 +280,15 @@ public:
     return getInstrRUsage(opCode).numBubbles;
   }
   
+  inline unsigned getCPUResourceNum(int rd)const{
+    for(unsigned i=0;i<resourceNumVector.size();i++){
+      if(resourceNumVector[i].first == rd) return resourceNumVector[i].second;
+    }
+    assert( 0&&"resource not found");
+    return 0;
+  }
+  
+
 protected:
   virtual void initializeResources     ();
   
@@ -276,19 +296,37 @@ private:
   void computeInstrResources(const std::vector<InstrRUsage>& instrRUForClasses);
   void computeIssueGaps(const std::vector<InstrRUsage>& instrRUForClasses);
   
+  void setGap(int gap, MachineOpCode fromOp, MachineOpCode toOp) {
+    std::vector<int>& toGaps = issueGaps[fromOp];
+    if (toOp >= (int) toGaps.size())
+      toGaps.resize(toOp+1);
+    toGaps[toOp] = gap;
+  }
+  
+public:
+  std::vector<std::pair<int,int> > resourceNumVector;
+  
 protected:
-  int                     numSchedClasses;
-  const MachineInstrInfo*  mii;
+  unsigned                numSchedClasses;
+  const TargetInstrInfo*   mii;
   const        InstrClassRUsage*  classRUsages;        // raw array by sclass
   const        InstrRUsageDelta*  usageDeltas;         // raw array [1:numUsageDeltas]
   const InstrIssueDelta*   issueDeltas;                // raw array [1:numIssueDeltas]
   unsigned                numUsageDeltas;
   unsigned                numIssueDeltas;
   
-  std::vector<InstrRUsage>      instrRUsages;   // indexed by opcode
-  hash_map<OpCodePair,int> issueGaps;      // indexed by opcode pair
-  hash_map<MachineOpCode, std::vector<MachineOpCode> >
-                          conflictLists;       // indexed by opcode
+  std::vector<InstrRUsage> instrRUsages;    // indexed by opcode
+  std::vector<std::vector<int> > issueGaps; // indexed by [opcode1][opcode2]
+  std::vector<std::vector<MachineOpCode> >
+                          conflictLists;   // indexed by [opcode]
+
+
+
+  friend class ModuloSchedGraph;
+  friend class ModuloScheduling;
+  
 };
 
+} // End llvm namespace
+
 #endif