-//===-- llvm/Target/SchedInfo.h - Target Instruction Sched Info --*- C++ -*-==//
+//===- Target/TargetSchedInfo.h - Target Instruction Sched Info -*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
//
// This file describes the target machine to the instruction scheduler.
//
+// NOTE: This file is currently sparc V9 specific.
+//
//===----------------------------------------------------------------------===//
-#ifndef LLVM_TARGET_MACHINESCHEDINFO_H
-#define LLVM_TARGET_MACHINESCHEDINFO_H
+#ifndef LLVM_TARGET_TARGETSCHEDINFO_H
+#define LLVM_TARGET_TARGETSCHEDINFO_H
-#include "llvm/Target/MachineInstrInfo.h"
-#include <ext/hash_map>
+#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/ADT/hash_map"
+#include <string>
-typedef long long cycles_t;
-const cycles_t HUGE_LATENCY = ~((unsigned long long) 1 << sizeof(cycles_t)-2);
-const cycles_t INVALID_LATENCY = -HUGE_LATENCY;
-static const unsigned MAX_OPCODE_SIZE = 16;
+namespace llvm {
-class OpCodePair {
-public:
- long val; // make long by concatenating two opcodes
- OpCodePair(MachineOpCode op1, MachineOpCode op2)
- : val((op1 < 0 || op2 < 0)?
- -1 : (long)((((unsigned) op1) << MAX_OPCODE_SIZE) | (unsigned) op2)) {}
- bool operator==(const OpCodePair& op) const {
- return val == op.val;
- }
-private:
- OpCodePair(); // disable for now
-};
-
-namespace std {
-template <> struct hash<OpCodePair> {
- size_t operator()(const OpCodePair& pair) const {
- return hash<long>()(pair.val);
- }
-};
-}
+typedef long long CycleCount_t;
+static const CycleCount_t HUGE_LATENCY = ~((long long) 1 << (sizeof(CycleCount_t)-2));
+static const CycleCount_t INVALID_LATENCY = -HUGE_LATENCY;
//---------------------------------------------------------------------------
// class MachineResource
//---------------------------------------------------------------------------
-typedef unsigned int resourceId_t;
+typedef unsigned resourceId_t;
-class MachineResource {
-public:
+struct CPUResource {
const std::string rname;
resourceId_t rid;
+ int maxNumUsers; // MAXINT if no restriction
- /*ctor*/ MachineResource(const std::string& resourceName)
- : rname(resourceName), rid(nextId++) {}
-
+ CPUResource(const std::string& resourceName, int maxUsers);
+ static CPUResource* getCPUResource(resourceId_t id);
private:
static resourceId_t nextId;
- MachineResource(); // disable
-};
-
-
-class CPUResource : public MachineResource {
-public:
- int maxNumUsers; // MAXINT if no restriction
-
- /*ctor*/ CPUResource(const std::string& rname, int maxUsers)
- : MachineResource(rname), maxNumUsers(maxUsers) {}
};
int totCycles;
// Issue restrictions common to instructions in this class
- unsigned int maxNumIssue;
- bool isSingleIssue;
- bool breaksGroup;
- cycles_t numBubbles;
+ unsigned maxNumIssue;
+ bool isSingleIssue;
+ bool breaksGroup;
+ CycleCount_t numBubbles;
// Feasible slots to use for instructions in this class.
// The size of vector S[] is `numSlots'.
- unsigned int numSlots;
- unsigned int feasibleSlots[MAX_NUM_SLOTS];
+ unsigned numSlots;
+ unsigned feasibleSlots[MAX_NUM_SLOTS];
// Resource usages common to instructions in this class.
// The size of vector V[] is `numRUEntries'.
- unsigned int numRUEntries;
+ unsigned numRUEntries;
struct {
resourceId_t resourceId;
- unsigned int startCycle;
- int numCycles;
- } V[MAX_NUM_CYCLES];
+ unsigned startCycle;
+ int numCycles;
+ } V[MAX_NUM_CYCLES];
};
struct InstrRUsageDelta {
MachineOpCode opCode;
resourceId_t resourceId;
- unsigned int startCycle;
+ unsigned startCycle;
int numCycles;
};
MachineOpCode opCode;
bool isSingleIssue;
bool breaksGroup;
- cycles_t numBubbles;
+ CycleCount_t numBubbles;
};
struct InstrRUsage {
- /*ctor*/ InstrRUsage () {}
- /*ctor*/ InstrRUsage (const InstrRUsage& instrRU);
- InstrRUsage& operator= (const InstrRUsage& instrRU);
-
bool sameAsClass;
// Issue restrictions for this instruction
bool isSingleIssue;
bool breaksGroup;
- cycles_t numBubbles;
+ CycleCount_t numBubbles;
// Feasible slots to use for this instruction.
std::vector<bool> feasibleSlots;
// Resource usages for this instruction, with one resource vector per cycle.
- cycles_t numCycles;
+ CycleCount_t numCycles;
std::vector<std::vector<resourceId_t> > resourcesByCycle;
private:
// Conveniences for initializing this structure
- InstrRUsage& operator= (const InstrClassRUsage& classRU);
- void addIssueDelta (const InstrIssueDelta& delta);
- void addUsageDelta (const InstrRUsageDelta& delta);
- void setMaxSlots (int maxNumSlots);
-
- friend class MachineSchedInfo; // give access to these functions
-};
-
-
-inline void
-InstrRUsage::setMaxSlots(int maxNumSlots)
-{
- feasibleSlots.resize(maxNumSlots);
-}
+ void setTo(const InstrClassRUsage& classRU);
-inline InstrRUsage&
-InstrRUsage::operator=(const InstrRUsage& instrRU)
-{
- sameAsClass = instrRU.sameAsClass;
- isSingleIssue = instrRU.isSingleIssue;
- breaksGroup = instrRU.breaksGroup;
- numBubbles = instrRU.numBubbles;
- feasibleSlots = instrRU.feasibleSlots;
- numCycles = instrRU.numCycles;
- resourcesByCycle = instrRU.resourcesByCycle;
- return *this;
-}
-
-inline /*ctor*/
-InstrRUsage::InstrRUsage(const InstrRUsage& instrRU)
-{
- *this = instrRU;
-}
+ void addIssueDelta(const InstrIssueDelta& delta) {
+ sameAsClass = false;
+ isSingleIssue = delta.isSingleIssue;
+ breaksGroup = delta.breaksGroup;
+ numBubbles = delta.numBubbles;
+ }
-inline InstrRUsage&
-InstrRUsage::operator=(const InstrClassRUsage& classRU)
-{
- sameAsClass = true;
- isSingleIssue = classRU.isSingleIssue;
- breaksGroup = classRU.breaksGroup;
- numBubbles = classRU.numBubbles;
-
- for (unsigned i=0; i < classRU.numSlots; i++)
- {
- unsigned slot = classRU.feasibleSlots[i];
- assert(slot < feasibleSlots.size() && "Invalid slot specified!");
- this->feasibleSlots[slot] = true;
- }
-
- this->numCycles = classRU.totCycles;
- this->resourcesByCycle.resize(this->numCycles);
-
- for (unsigned i=0; i < classRU.numRUEntries; i++)
- for (unsigned c=classRU.V[i].startCycle, NC = c + classRU.V[i].numCycles;
- c < NC; c++)
- this->resourcesByCycle[c].push_back(classRU.V[i].resourceId);
-
- // Sort each resource usage vector by resourceId_t to speed up conflict checking
- for (unsigned i=0; i < this->resourcesByCycle.size(); i++)
- sort(resourcesByCycle[i].begin(), resourcesByCycle[i].end());
+ void addUsageDelta (const InstrRUsageDelta& delta);
+ void setMaxSlots (int maxNumSlots) {
+ feasibleSlots.resize(maxNumSlots);
+ }
- return *this;
-}
-
-
-inline void
-InstrRUsage::addIssueDelta(const InstrIssueDelta& delta)
-{
- sameAsClass = false;
- isSingleIssue = delta.isSingleIssue;
- breaksGroup = delta.breaksGroup;
- numBubbles = delta.numBubbles;
-}
+ friend class TargetSchedInfo; // give access to these functions
+};
-// Add the extra resource usage requirements specified in the delta.
-// Note that a negative value of `numCycles' means one entry for that
-// resource should be deleted for each cycle.
-//
-inline void
-InstrRUsage::addUsageDelta(const InstrRUsageDelta& delta)
-{
- int NC = delta.numCycles;
-
- this->sameAsClass = false;
-
- // resize the resources vector if more cycles are specified
- unsigned maxCycles = this->numCycles;
- maxCycles = std::max(maxCycles, delta.startCycle + abs(NC) - 1);
- if (maxCycles > this->numCycles)
- {
- this->resourcesByCycle.resize(maxCycles);
- this->numCycles = maxCycles;
- }
-
- if (NC >= 0)
- for (unsigned c=delta.startCycle, last=c+NC-1; c <= last; c++)
- this->resourcesByCycle[c].push_back(delta.resourceId);
- else
- // Remove the resource from all NC cycles.
- for (unsigned c=delta.startCycle, last=(c-NC)-1; c <= last; c++)
- {
- // Look for the resource backwards so we remove the last entry
- // for that resource in each cycle.
- std::vector<resourceId_t>& rvec = this->resourcesByCycle[c];
- int r;
- for (r = (int) rvec.size(); r >= 0; r--)
- if (rvec[r] == delta.resourceId)
- {// found last entry for the resource
- rvec.erase(rvec.begin() + r);
- break;
- }
- assert(r >= 0 && "Resource to remove was unused in cycle c!");
- }
-}
-
//---------------------------------------------------------------------------
-// class MachineSchedInfo
-//
-// Purpose:
-// Common interface to machine information for instruction scheduling
-//---------------------------------------------------------------------------
-
-class MachineSchedInfo : public NonCopyableV {
+/// TargetSchedInfo - Common interface to machine information for
+/// instruction scheduling
+///
+class TargetSchedInfo {
public:
const TargetMachine& target;
- unsigned int maxNumIssueTotal;
+ unsigned maxNumIssueTotal;
int longestIssueConflict;
- int branchMispredictPenalty; // 4 for SPARC IIi
- int branchTargetUnknownPenalty; // 2 for SPARC IIi
- int l1DCacheMissPenalty; // 7 or 9 for SPARC IIi
- int l1ICacheMissPenalty; // ? for SPARC IIi
-
- bool inOrderLoads; // true for SPARC IIi
- bool inOrderIssue; // true for SPARC IIi
- bool inOrderExec; // false for most architectures
- bool inOrderRetire; // true for most architectures
-
protected:
inline const InstrRUsage& getInstrRUsage(MachineOpCode opCode) const {
assert(opCode >= 0 && opCode < (int) instrRUsages.size());
return instrRUsages[opCode];
}
- inline const InstrClassRUsage&
- getClassRUsage(const InstrSchedClass& sc) const {
- assert(sc >= 0 && sc < numSchedClasses);
+ const InstrClassRUsage& getClassRUsage(const InstrSchedClass& sc) const {
+ assert(sc < numSchedClasses);
return classRUsages[sc];
}
-
+
+private:
+ TargetSchedInfo(const TargetSchedInfo &); // DO NOT IMPLEMENT
+ void operator=(const TargetSchedInfo &); // DO NOT IMPLEMENT
public:
- /*ctor*/ MachineSchedInfo (const TargetMachine& tgt,
+ /*ctor*/ TargetSchedInfo (const TargetMachine& tgt,
int _numSchedClasses,
const InstrClassRUsage* _classRUsages,
const InstrRUsageDelta* _usageDeltas,
const InstrIssueDelta* _issueDeltas,
- unsigned int _numUsageDeltas,
- unsigned int _numIssueDeltas);
- /*dtor*/ virtual ~MachineSchedInfo () {}
+ unsigned _numUsageDeltas,
+ unsigned _numIssueDeltas);
+ /*dtor*/ virtual ~TargetSchedInfo() {}
- inline const MachineInstrInfo& getInstrInfo() const {
+ inline const TargetInstrInfo& getInstrInfo() const {
return *mii;
}
return numSchedClasses;
}
- inline unsigned int getMaxNumIssueTotal() const {
+ inline unsigned getMaxNumIssueTotal() const {
return maxNumIssueTotal;
}
- inline unsigned int getMaxIssueForClass(const InstrSchedClass& sc) const {
- assert(sc >= 0 && sc < numSchedClasses);
+ inline unsigned getMaxIssueForClass(const InstrSchedClass& sc) const {
+ assert(sc < numSchedClasses);
return classRUsages[sc].maxNumIssue;
}
inline int getLongestIssueConflict () const {
return longestIssueConflict;
}
-
+
inline int getMinIssueGap (MachineOpCode fromOp,
MachineOpCode toOp) const {
- std::hash_map<OpCodePair,int>::const_iterator
- I = issueGaps.find(OpCodePair(fromOp, toOp));
- return (I == issueGaps.end())? 0 : (*I).second;
+ assert(fromOp < (int) issueGaps.size());
+ const std::vector<int>& toGaps = issueGaps[fromOp];
+ return (toOp < (int) toGaps.size())? toGaps[toOp] : 0;
}
-
- inline const std::vector<MachineOpCode>*
+
+ inline const std::vector<MachineOpCode>&
getConflictList(MachineOpCode opCode) const {
- std::hash_map<MachineOpCode, std::vector<MachineOpCode> >::const_iterator
- I = conflictLists.find(opCode);
- return (I == conflictLists.end())? NULL : & (*I).second;
+ assert(opCode < (int) conflictLists.size());
+ return conflictLists[opCode];
}
-
+
inline bool isSingleIssue (MachineOpCode opCode) const {
return getInstrRUsage(opCode).isSingleIssue;
}
return getInstrRUsage(opCode).breaksGroup;
}
- inline unsigned int numBubblesAfter (MachineOpCode opCode) const {
+ inline unsigned numBubblesAfter (MachineOpCode opCode) const {
return getInstrRUsage(opCode).numBubbles;
}
+ inline unsigned getCPUResourceNum(int rd)const{
+ for(unsigned i=0;i<resourceNumVector.size();i++){
+ if(resourceNumVector[i].first == rd) return resourceNumVector[i].second;
+ }
+ assert( 0&&"resource not found");
+ return 0;
+ }
+
+
protected:
virtual void initializeResources ();
void computeInstrResources(const std::vector<InstrRUsage>& instrRUForClasses);
void computeIssueGaps(const std::vector<InstrRUsage>& instrRUForClasses);
+ void setGap(int gap, MachineOpCode fromOp, MachineOpCode toOp) {
+ std::vector<int>& toGaps = issueGaps[fromOp];
+ if (toOp >= (int) toGaps.size())
+ toGaps.resize(toOp+1);
+ toGaps[toOp] = gap;
+ }
+
+public:
+ std::vector<std::pair<int,int> > resourceNumVector;
+
protected:
- int numSchedClasses;
- const MachineInstrInfo* mii;
+ unsigned numSchedClasses;
+ const TargetInstrInfo* mii;
const InstrClassRUsage* classRUsages; // raw array by sclass
const InstrRUsageDelta* usageDeltas; // raw array [1:numUsageDeltas]
const InstrIssueDelta* issueDeltas; // raw array [1:numIssueDeltas]
- unsigned int numUsageDeltas;
- unsigned int numIssueDeltas;
+ unsigned numUsageDeltas;
+ unsigned numIssueDeltas;
+
+ std::vector<InstrRUsage> instrRUsages; // indexed by opcode
+ std::vector<std::vector<int> > issueGaps; // indexed by [opcode1][opcode2]
+ std::vector<std::vector<MachineOpCode> >
+ conflictLists; // indexed by [opcode]
+
+
+ friend class ModuloSchedulingPass;
+ friend class MSSchedule;
- std::vector<InstrRUsage> instrRUsages; // indexed by opcode
- std::hash_map<OpCodePair,int> issueGaps; // indexed by opcode pair
- std::hash_map<MachineOpCode, std::vector<MachineOpCode> >
- conflictLists; // indexed by opcode
};
+} // End llvm namespace
+
#endif
projects / oota-llvm.git / blobdiff