Capture information about whether the target instructions have delay slots

[oota-llvm.git] / include / llvm / Target / TargetSchedInfo.h

diff --git a/include/llvm/Target/TargetSchedInfo.h b/include/llvm/Target/TargetSchedInfo.h
index 293835cefa64ba48c79fb12e5f7ba20471e38cb3..f2a3560496cd1239690380858fa94d328d21c973 100644 (file)
--- a/include/llvm/Target/TargetSchedInfo.h
+++ b/include/llvm/Target/TargetSchedInfo.h
@@ -1,16 +1,27 @@
-//===- Target/MachineSchedInfo.h - Target Instruction Sched Info -*- C++ -*-==//
+//===- Target/TargetSchedInfo.h - Target Instruction Sched Info -*- C++ -*-===//
+// 
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// 
+//===----------------------------------------------------------------------===//
 //
 // This file describes the target machine to the instruction scheduler.
 //
+// NOTE: This file is currently sparc V9 specific.
+//
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_TARGET_MACHINESCHEDINFO_H
-#define LLVM_TARGET_MACHINESCHEDINFO_H
+#ifndef LLVM_TARGET_TARGETSCHEDINFO_H
+#define LLVM_TARGET_TARGETSCHEDINFO_H
 
-#include "llvm/Target/MachineInstrInfo.h"
-#include "Support/hash_map"
+#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/ADT/hash_map"
 #include <string>
 
+namespace llvm {
+
 typedef long long cycles_t; 
 static const cycles_t HUGE_LATENCY = ~((long long) 1 << (sizeof(cycles_t)-2));
 static const cycles_t INVALID_LATENCY = -HUGE_LATENCY; 
@@ -29,13 +40,17 @@ private:
   OpCodePair();                        // disable for now
 };
 
+} // End llvm namespace
+
 namespace HASH_NAMESPACE {
-  template <> struct hash<OpCodePair> {
-    size_t operator()(const OpCodePair& pair) const {
+  template <> struct hash<llvm::OpCodePair> {
+    size_t operator()(const llvm::OpCodePair& pair) const {
       return hash<long>()(pair.val);
     }
   };
-}
+} // End HASH_NAMESPACE (a macro) namespace
+
+namespace llvm {
 
 //---------------------------------------------------------------------------
 // class MachineResource 
@@ -49,24 +64,15 @@ namespace HASH_NAMESPACE {
 
 typedef unsigned resourceId_t;
 
-struct MachineResource {
+struct CPUResource {
   const std::string rname;
   resourceId_t rid;
+  int maxNumUsers;   // MAXINT if no restriction
   
-  MachineResource(const std::string &resourceName)
-    : rname(resourceName), rid(nextId++) {}
-  
+  CPUResource(const std::string& resourceName, int maxUsers);
+  static CPUResource* getCPUResource(resourceId_t id);
 private:
   static resourceId_t nextId;
-  MachineResource();                   // disable
-};
-
-
-struct CPUResource : public MachineResource {
-  int maxNumUsers;   // MAXINT if no restriction
-  
-  CPUResource(const std::string& rname, int maxUsers)
-    : MachineResource(rname), maxNumUsers(maxUsers) {}
 };
 
 
@@ -164,34 +170,20 @@ private:
     feasibleSlots.resize(maxNumSlots);
   }
   
-  friend class MachineSchedInfo;       // give access to these functions
+  friend class TargetSchedInfo;        // give access to these functions
 };
 
 
 //---------------------------------------------------------------------------
-// class MachineSchedInfo
-//
-// Purpose:
-//   Common interface to machine information for instruction scheduling
-//---------------------------------------------------------------------------
-
-class MachineSchedInfo {
-public:
+/// TargetSchedInfo - Common interface to machine information for 
+/// instruction scheduling
+///
+struct TargetSchedInfo {
   const TargetMachine& target;
   
   unsigned maxNumIssueTotal;
   int  longestIssueConflict;
   
-  int  branchMispredictPenalty;        // 4 for SPARC IIi
-  int  branchTargetUnknownPenalty;     // 2 for SPARC IIi
-  int   l1DCacheMissPenalty;           // 7 or 9 for SPARC IIi
-  int   l1ICacheMissPenalty;           // ? for SPARC IIi
-  
-  bool inOrderLoads;                   // true for SPARC IIi
-  bool inOrderIssue;                   // true for SPARC IIi
-  bool inOrderExec;                    // false for most architectures
-  bool inOrderRetire;                  // true for most architectures
-  
 protected:
   inline const InstrRUsage& getInstrRUsage(MachineOpCode opCode) const {
     assert(opCode >= 0 && opCode < (int) instrRUsages.size());
@@ -203,19 +195,19 @@ protected:
   }
 
 private:
-  MachineSchedInfo(const MachineSchedInfo &);  // DO NOT IMPLEMENT
-  void operator=(const MachineSchedInfo &);  // DO NOT IMPLEMENT
+  TargetSchedInfo(const TargetSchedInfo &);  // DO NOT IMPLEMENT
+  void operator=(const TargetSchedInfo &);  // DO NOT IMPLEMENT
 public:
-  /*ctor*/        MachineSchedInfo     (const TargetMachine& tgt,
+  /*ctor*/        TargetSchedInfo      (const TargetMachine& tgt,
                                          int                  _numSchedClasses,
                                         const InstrClassRUsage* _classRUsages,
                                         const InstrRUsageDelta* _usageDeltas,
                                         const InstrIssueDelta*  _issueDeltas,
                                         unsigned _numUsageDeltas,
                                         unsigned _numIssueDeltas);
-  /*dtor*/ virtual ~MachineSchedInfo   () {}
+  /*dtor*/ virtual ~TargetSchedInfo() {}
   
-  inline const MachineInstrInfo& getInstrInfo() const {
+  inline const TargetInstrInfo& getInstrInfo() const {
     return *mii;
   }
   
@@ -271,6 +263,15 @@ public:
     return getInstrRUsage(opCode).numBubbles;
   }
   
+  inline unsigned getCPUResourceNum(int rd)const{
+    for(unsigned i=0;i<resourceNumVector.size();i++){
+      if(resourceNumVector[i].first == rd) return resourceNumVector[i].second;
+    }
+    assert( 0&&"resource not found");
+    return 0;
+  }
+  
+
 protected:
   virtual void initializeResources     ();
   
@@ -285,9 +286,12 @@ private:
     toGaps[toOp] = gap;
   }
   
+public:
+  std::vector<std::pair<int,int> > resourceNumVector;
+  
 protected:
   unsigned                numSchedClasses;
-  const MachineInstrInfo*  mii;
+  const TargetInstrInfo*   mii;
   const        InstrClassRUsage*  classRUsages;        // raw array by sclass
   const        InstrRUsageDelta*  usageDeltas;         // raw array [1:numUsageDeltas]
   const InstrIssueDelta*   issueDeltas;                // raw array [1:numIssueDeltas]
@@ -298,6 +302,13 @@ protected:
   std::vector<std::vector<int> > issueGaps; // indexed by [opcode1][opcode2]
   std::vector<std::vector<MachineOpCode> >
                           conflictLists;   // indexed by [opcode]
+
+
+  friend class ModuloSchedulingPass;
+  friend class MSSchedule;
+  
 };
 
+} // End llvm namespace
+
 #endif