-//===- Target/TargetSchedInfo.h - Target Instruction Sched Info --*- C++ -*-==//
+//===- Target/TargetSchedInfo.h - Target Instruction Sched Info -*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
//
// This file describes the target machine to the instruction scheduler.
//
#include "llvm/Target/TargetInstrInfo.h"
#include "Support/hash_map"
#include <string>
-#include <assert.h>
+
+namespace llvm {
typedef long long cycles_t;
static const cycles_t HUGE_LATENCY = ~((long long) 1 << (sizeof(cycles_t)-2));
OpCodePair(); // disable for now
};
+} // End llvm namespace
+
namespace HASH_NAMESPACE {
- template <> struct hash<OpCodePair> {
- size_t operator()(const OpCodePair& pair) const {
+ template <> struct hash<llvm::OpCodePair> {
+ size_t operator()(const llvm::OpCodePair& pair) const {
return hash<long>()(pair.val);
}
};
-}
+} // End HASH_NAMESPACE (a macro) namespace
+
+namespace llvm {
//---------------------------------------------------------------------------
// class MachineResource
typedef unsigned resourceId_t;
-struct MachineResource {
+struct CPUResource {
const std::string rname;
resourceId_t rid;
+ int maxNumUsers; // MAXINT if no restriction
- MachineResource(const std::string &resourceName)
- : rname(resourceName), rid(nextId++) {}
-
+ CPUResource(const std::string& resourceName, int maxUsers);
+
private:
static resourceId_t nextId;
- MachineResource(); // disable
-};
-
-
-struct CPUResource : public MachineResource {
- int maxNumUsers; // MAXINT if no restriction
-
- CPUResource(const std::string& rname, int maxUsers)
- : MachineResource(rname), maxNumUsers(maxUsers) {}
};
unsigned maxNumIssueTotal;
int longestIssueConflict;
- int branchMispredictPenalty; // 4 for SPARC IIi
- int branchTargetUnknownPenalty; // 2 for SPARC IIi
- int l1DCacheMissPenalty; // 7 or 9 for SPARC IIi
- int l1ICacheMissPenalty; // ? for SPARC IIi
-
- bool inOrderLoads; // true for SPARC IIi
- bool inOrderIssue; // true for SPARC IIi
- bool inOrderExec; // false for most architectures
- bool inOrderRetire; // true for most architectures
-
protected:
inline const InstrRUsage& getInstrRUsage(MachineOpCode opCode) const {
assert(opCode >= 0 && opCode < (int) instrRUsages.size());
conflictLists; // indexed by [opcode]
-
friend class ModuloSchedGraph;
- friend class ModuloScheduling;
+ friend class ModuloSchedulingPass;
};
+} // End llvm namespace
+
#endif