assert(0) -> LLVM_UNREACHABLE.

[oota-llvm.git] / include / llvm / Target / TargetSelectionDAG.td

diff --git a/include/llvm/Target/TargetSelectionDAG.td b/include/llvm/Target/TargetSelectionDAG.td
index 2586e65d3971e7221ebfbabae0a0de9864627c63..364d4d0d3cc0f439aa68afbf7da4d0d44a9609d6 100644 (file)
--- a/include/llvm/Target/TargetSelectionDAG.td
+++ b/include/llvm/Target/TargetSelectionDAG.td
@@ -216,8 +216,6 @@ def SDNPMayStore    : SDNodeProperty;   // May write to memory, sets 'mayStore'.
 def SDNPMayLoad     : SDNodeProperty;   // May read memory, sets 'mayLoad'.
 def SDNPSideEffect  : SDNodeProperty;   // Sets 'HasUnmodelledSideEffects'.
 def SDNPMemOperand  : SDNodeProperty;   // Touches memory, has assoc MemOperand
-def SDNPInI1        : SDNodeProperty;   // Read an extra I1 operand
-def SDNPOutI1       : SDNodeProperty;   // Write an extra I1 result
 
 //===----------------------------------------------------------------------===//
 // Selection DAG Node definitions.
@@ -230,6 +228,7 @@ class SDNode<string opcode, SDTypeProfile typeprof,
   SDTypeProfile TypeProfile = typeprof;
 }
 
+// Special TableGen-recognized dag nodes
 def set;
 def implicit;
 def parallel;
@@ -291,13 +290,13 @@ def or         : SDNode<"ISD::OR"        , SDTIntBinOp,
 def xor        : SDNode<"ISD::XOR"       , SDTIntBinOp,
                         [SDNPCommutative, SDNPAssociative]>;
 def addc       : SDNode<"ISD::ADDC"      , SDTIntBinOp,
-                        [SDNPCommutative, SDNPOutI1]>;
+                        [SDNPCommutative, SDNPOutFlag]>;
 def adde       : SDNode<"ISD::ADDE"      , SDTIntBinOp,
-                        [SDNPCommutative, SDNPInI1, SDNPOutI1]>;
+                        [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>;
 def subc       : SDNode<"ISD::SUBC"      , SDTIntBinOp,
-                        [SDNPOutI1]>;
+                        [SDNPOutFlag]>;
 def sube       : SDNode<"ISD::SUBE"      , SDTIntBinOp,
-                        [SDNPInI1, SDNPOutI1]>;
+                        [SDNPOutFlag, SDNPInFlag]>;
                         
 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
 def bswap      : SDNode<"ISD::BSWAP"      , SDTIntUnaryOp>;