#ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H
#define LLVM_TARGET_TARGETSUBTARGETINFO_H
-#include "llvm/CodeGen/TargetSchedule.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/CodeGen.h"
namespace llvm {
+class MachineFunction;
+class MachineInstr;
class SDep;
class SUnit;
class TargetRegisterClass;
+class TargetSchedModel;
+struct MachineSchedPolicy;
template <typename T> class SmallVectorImpl;
//===----------------------------------------------------------------------===//
virtual ~TargetSubtargetInfo();
- /// Initialize a copy of the scheduling model for this subtarget.
- /// TargetSchedModel provides the interface for the subtarget's
- /// instruction scheduling information.
- void initSchedModel(TargetSchedModel &SchedModel,
- const TargetInstrInfo *TII) const {
- // CPUSchedModel is initialized to a static instance by InitMCSubtargetInfo.
- SchedModel.init(*getSchedModel(), this, TII);
- }
-
/// Resolve a SchedClass at runtime, where SchedClass identifies an
/// MCSchedClassDesc with the isVariant property. This may return the ID of
/// another variant SchedClass, but repeated invocation must quickly terminate
return 0;
}
- /// getSpecialAddressLatency - For targets where it is beneficial to
- /// backschedule instructions that compute addresses, return a value
- /// indicating the number of scheduling cycles of backscheduling that
- /// should be attempted.
- virtual unsigned getSpecialAddressLatency() const { return 0; }
-
- // enablePostRAScheduler - If the target can benefit from post-regalloc
- // scheduling and the specified optimization level meets the requirement
- // return true to enable post-register-allocation scheduling. In
- // CriticalPathRCs return any register classes that should only be broken
- // if on the critical path.
- virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
- AntiDepBreakMode& Mode,
- RegClassVector& CriticalPathRCs) const;
- // adjustSchedDependency - Perform target specific adjustments to
- // the latency of a schedule dependency.
+ /// \brief Temporary API to test migration to MI scheduler.
+ bool useMachineScheduler() const;
+
+ /// \brief True if the subtarget should run MachineScheduler after aggressive
+ /// coalescing.
+ ///
+ /// This currently replaces the SelectionDAG scheduler with the "source" order
+ /// scheduler. It does not yet disable the postRA scheduler.
+ virtual bool enableMachineScheduler() const;
+
+ /// \brief True if the subtarget should run PostMachineScheduler.
+ ///
+ /// This only takes effect if the target has configured the
+ /// PostMachineScheduler pass to run, or if the global cl::opt flag,
+ /// MISchedPostRA, is set.
+ virtual bool enablePostMachineScheduler() const;
+
+ /// \brief True if the subtarget should run the atomic expansion pass.
+ virtual bool enableAtomicExpandLoadLinked() const;
+
+ /// \brief Override generic scheduling policy within a region.
+ ///
+ /// This is a convenient way for targets that don't provide any custom
+ /// scheduling heuristics (no custom MachineSchedStrategy) to make
+ /// changes to the generic scheduling policy.
+ virtual void overrideSchedPolicy(MachineSchedPolicy &Policy,
+ MachineInstr *begin,
+ MachineInstr *end,
+ unsigned NumRegionInstrs) const {}
+
+ // \brief Perform target specific adjustments to the latency of a schedule
+ // dependency.
virtual void adjustSchedDependency(SUnit *def, SUnit *use,
SDep& dep) const { }
+
+ // For use with PostRAScheduling: get the anti-dependence breaking that should
+ // be performed before post-RA scheduling.
+ virtual AntiDepBreakMode getAntiDepBreakMode() const {
+ return ANTIDEP_NONE;
+ }
+
+ // For use with PostRAScheduling: in CriticalPathRCs, return any register
+ // classes that should only be considered for anti-dependence breaking if they
+ // are on the critical path.
+ virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
+ return CriticalPathRCs.clear();
+ }
+
+ // For use with PostRAScheduling: get the minimum optimization level needed
+ // to enable post-RA scheduling.
+ virtual CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const {
+ return CodeGenOpt::Default;
+ }
+
+ /// \brief True if the subtarget should run the local reassignment
+ /// heuristic of the register allocator.
+ /// This heuristic may be compile time intensive, \p OptLevel provides
+ /// a finer grain to tune the register allocator.
+ virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const;
+
+ /// \brief Enable use of alias analysis during code generation (during MI
+ /// scheduling, DAGCombine, etc.).
+ virtual bool useAA() const;
+
+ /// \brief Enable the use of the early if conversion pass.
+ virtual bool enableEarlyIfConversion() const { return false; }
+
+ /// \brief Reset the features for the subtarget.
+ virtual void resetSubtargetFeatures(const MachineFunction *MF) { }
+
};
} // End llvm namespace