Merge branches 'acpi-scan', 'acpi-utils' and 'acpi-pm'

[firefly-linux-kernel-4.4.55.git] / kernel / irq / generic-chip.c

diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c
index cf80e7b0ddab6b1b451dfa8a1fc66a6d97492cea..61024e8abdeffdeff717d389ddbe8fd99110532c 100644 (file)
--- a/kernel/irq/generic-chip.c
+++ b/kernel/irq/generic-chip.c
@@ -39,7 +39,7 @@ void irq_gc_mask_disable_reg(struct irq_data *d)
        u32 mask = d->mask;
 
        irq_gc_lock(gc);
-       irq_reg_writel(mask, gc->reg_base + ct->regs.disable);
+       irq_reg_writel(gc, mask, ct->regs.disable);
        *ct->mask_cache &= ~mask;
        irq_gc_unlock(gc);
 }
@@ -59,7 +59,7 @@ void irq_gc_mask_set_bit(struct irq_data *d)
 
        irq_gc_lock(gc);
        *ct->mask_cache |= mask;
-       irq_reg_writel(*ct->mask_cache, gc->reg_base + ct->regs.mask);
+       irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
        irq_gc_unlock(gc);
 }
 EXPORT_SYMBOL_GPL(irq_gc_mask_set_bit);
@@ -79,7 +79,7 @@ void irq_gc_mask_clr_bit(struct irq_data *d)
 
        irq_gc_lock(gc);
        *ct->mask_cache &= ~mask;
-       irq_reg_writel(*ct->mask_cache, gc->reg_base + ct->regs.mask);
+       irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
        irq_gc_unlock(gc);
 }
 EXPORT_SYMBOL_GPL(irq_gc_mask_clr_bit);
@@ -98,7 +98,7 @@ void irq_gc_unmask_enable_reg(struct irq_data *d)
        u32 mask = d->mask;
 
        irq_gc_lock(gc);
-       irq_reg_writel(mask, gc->reg_base + ct->regs.enable);
+       irq_reg_writel(gc, mask, ct->regs.enable);
        *ct->mask_cache |= mask;
        irq_gc_unlock(gc);
 }
@@ -114,7 +114,7 @@ void irq_gc_ack_set_bit(struct irq_data *d)
        u32 mask = d->mask;
 
        irq_gc_lock(gc);
-       irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
+       irq_reg_writel(gc, mask, ct->regs.ack);
        irq_gc_unlock(gc);
 }
 EXPORT_SYMBOL_GPL(irq_gc_ack_set_bit);
@@ -130,7 +130,7 @@ void irq_gc_ack_clr_bit(struct irq_data *d)
        u32 mask = ~d->mask;
 
        irq_gc_lock(gc);
-       irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
+       irq_reg_writel(gc, mask, ct->regs.ack);
        irq_gc_unlock(gc);
 }
 
@@ -145,8 +145,8 @@ void irq_gc_mask_disable_reg_and_ack(struct irq_data *d)
        u32 mask = d->mask;
 
        irq_gc_lock(gc);
-       irq_reg_writel(mask, gc->reg_base + ct->regs.mask);
-       irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
+       irq_reg_writel(gc, mask, ct->regs.mask);
+       irq_reg_writel(gc, mask, ct->regs.ack);
        irq_gc_unlock(gc);
 }
 
@@ -161,7 +161,7 @@ void irq_gc_eoi(struct irq_data *d)
        u32 mask = d->mask;
 
        irq_gc_lock(gc);
-       irq_reg_writel(mask, gc->reg_base + ct->regs.eoi);
+       irq_reg_writel(gc, mask, ct->regs.eoi);
        irq_gc_unlock(gc);
 }
 
@@ -191,6 +191,16 @@ int irq_gc_set_wake(struct irq_data *d, unsigned int on)
        return 0;
 }
 
+static u32 irq_readl_be(void __iomem *addr)
+{
+       return ioread32be(addr);
+}
+
+static void irq_writel_be(u32 val, void __iomem *addr)
+{
+       iowrite32be(val, addr);
+}
+
 static void
 irq_init_generic_chip(struct irq_chip_generic *gc, const char *name,
                      int num_ct, unsigned int irq_base,
@@ -245,7 +255,7 @@ irq_gc_init_mask_cache(struct irq_chip_generic *gc, enum irq_gc_flags flags)
                }
                ct[i].mask_cache = mskptr;
                if (flags & IRQ_GC_INIT_MASK_CACHE)
-                       *mskptr = irq_reg_readl(gc->reg_base + mskreg);
+                       *mskptr = irq_reg_readl(gc, mskreg);
        }
 }
 
@@ -300,7 +310,13 @@ int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
                dgc->gc[i] = gc = tmp;
                irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip,
                                      NULL, handler);
+
                gc->domain = d;
+               if (gcflags & IRQ_GC_BE_IO) {
+                       gc->reg_readl = &irq_readl_be;
+                       gc->reg_writel = &irq_writel_be;
+               }
+
                raw_spin_lock_irqsave(&gc_lock, flags);
                list_add_tail(&gc->list, &gc_list);
                raw_spin_unlock_irqrestore(&gc_lock, flags);