-//===----- AggressiveAntiDepBreaker.cpp - Anti-dep breaker -------- ---------===//
+//===----- AggressiveAntiDepBreaker.cpp - Anti-dep breaker ----------------===//
//
// The LLVM Compiler Infrastructure
//
// If DebugDiv > 0 then only break antidep with (ID % DebugDiv) == DebugMod
static cl::opt<int>
DebugDiv("agg-antidep-debugdiv",
- cl::desc("Debug control for aggressive anti-dep breaker"),
- cl::init(0), cl::Hidden);
+ cl::desc("Debug control for aggressive anti-dep breaker"),
+ cl::init(0), cl::Hidden);
static cl::opt<int>
DebugMod("agg-antidep-debugmod",
- cl::desc("Debug control for aggressive anti-dep breaker"),
- cl::init(0), cl::Hidden);
-
-AggressiveAntiDepState::AggressiveAntiDepState(MachineBasicBlock *BB) :
- GroupNodes(TargetRegisterInfo::FirstVirtualRegister, 0) {
- // Initialize all registers to be in their own group. Initially we
- // assign the register to the same-indexed GroupNode.
- for (unsigned i = 0; i < TargetRegisterInfo::FirstVirtualRegister; ++i)
- GroupNodeIndices[i] = i;
+ cl::desc("Debug control for aggressive anti-dep breaker"),
+ cl::init(0), cl::Hidden);
+
+AggressiveAntiDepState::AggressiveAntiDepState(const unsigned TargetRegs,
+ MachineBasicBlock *BB) :
+ NumTargetRegs(TargetRegs), GroupNodes(TargetRegs, 0) {
- // Initialize the indices to indicate that no registers are live.
- std::fill(KillIndices, array_endof(KillIndices), ~0u);
- std::fill(DefIndices, array_endof(DefIndices), BB->size());
+ const unsigned BBSize = BB->size();
+ for (unsigned i = 0; i < NumTargetRegs; ++i) {
+ // Initialize all registers to be in their own group. Initially we
+ // assign the register to the same-indexed GroupNode.
+ GroupNodeIndices[i] = i;
+ // Initialize the indices to indicate that no registers are live.
+ KillIndices[i] = ~0u;
+ DefIndices[i] = BBSize;
+ }
}
unsigned AggressiveAntiDepState::GetGroup(unsigned Reg)
std::vector<unsigned> &Regs,
std::multimap<unsigned, AggressiveAntiDepState::RegisterReference> *RegRefs)
{
- for (unsigned Reg = 0; Reg != TargetRegisterInfo::FirstVirtualRegister; ++Reg) {
+ for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) {
if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
Regs.push_back(Reg);
}
{
assert(GroupNodes[0] == 0 && "GroupNode 0 not parent!");
assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
-
+
// find group for each register
unsigned Group1 = GetGroup(Reg1);
unsigned Group2 = GetGroup(Reg2);
-
+
// if either group is 0, then that must become the parent
unsigned Parent = (Group1 == 0) ? Group1 : Group2;
unsigned Other = (Parent == Group1) ? Group2 : Group1;
GroupNodes.at(Other) = Parent;
return Parent;
}
-
+
unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg)
{
// Create a new GroupNode for Reg. Reg's existing GroupNode must
AggressiveAntiDepBreaker::
AggressiveAntiDepBreaker(MachineFunction& MFi,
- TargetSubtarget::RegClassVector& CriticalPathRCs) :
+ TargetSubtarget::RegClassVector& CriticalPathRCs) :
AntiDepBreaker(), MF(MFi),
MRI(MF.getRegInfo()),
TRI(MF.getTarget().getRegisterInfo()),
else
CriticalPathSet |= CPSet;
}
-
- DEBUG(errs() << "AntiDep Critical-Path Registers:");
- DEBUG(for (int r = CriticalPathSet.find_first(); r != -1;
+
+ DEBUG(dbgs() << "AntiDep Critical-Path Registers:");
+ DEBUG(for (int r = CriticalPathSet.find_first(); r != -1;
r = CriticalPathSet.find_next(r))
- errs() << " " << TRI->getName(r));
- DEBUG(errs() << '\n');
+ dbgs() << " " << TRI->getName(r));
+ DEBUG(dbgs() << '\n');
}
AggressiveAntiDepBreaker::~AggressiveAntiDepBreaker() {
void AggressiveAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
assert(State == NULL);
- State = new AggressiveAntiDepState(BB);
+ State = new AggressiveAntiDepState(TRI->getNumRegs(), BB);
bool IsReturnBlock = (!BB->empty() && BB->back().getDesc().isReturn());
unsigned *KillIndices = State->GetKillIndices();
}
void AggressiveAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count,
- unsigned InsertPosIndex) {
+ unsigned InsertPosIndex) {
assert(Count < InsertPosIndex && "Instruction index out of expected range!");
std::set<unsigned> PassthruRegs;
PrescanInstruction(MI, Count, PassthruRegs);
ScanInstruction(MI, Count);
- DEBUG(errs() << "Observe: ");
+ DEBUG(dbgs() << "Observe: ");
DEBUG(MI->dump());
- DEBUG(errs() << "\tRegs:");
+ DEBUG(dbgs() << "\tRegs:");
unsigned *DefIndices = State->GetDefIndices();
- for (unsigned Reg = 0; Reg != TargetRegisterInfo::FirstVirtualRegister; ++Reg) {
+ for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
// If Reg is current live, then mark that it can't be renamed as
// we don't know the extent of its live-range anymore (now that it
// has been scheduled). If it is not live but was defined in the
// schedule region).
if (State->IsLive(Reg)) {
DEBUG(if (State->GetGroup(Reg) != 0)
- errs() << " " << TRI->getName(Reg) << "=g" <<
+ dbgs() << " " << TRI->getName(Reg) << "=g" <<
State->GetGroup(Reg) << "->g0(region live-out)");
State->UnionGroups(Reg, 0);
- } else if ((DefIndices[Reg] < InsertPosIndex) && (DefIndices[Reg] >= Count)) {
+ } else if ((DefIndices[Reg] < InsertPosIndex)
+ && (DefIndices[Reg] >= Count)) {
DefIndices[Reg] = Count;
}
}
- DEBUG(errs() << '\n');
+ DEBUG(dbgs() << '\n');
}
bool AggressiveAntiDepBreaker::IsImplicitDefUse(MachineInstr *MI,
- MachineOperand& MO)
+ MachineOperand& MO)
{
if (!MO.isReg() || !MO.isImplicit())
return false;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg()) continue;
- if ((MO.isDef() && MI->isRegTiedToUseOperand(i)) ||
+ if ((MO.isDef() && MI->isRegTiedToUseOperand(i)) ||
IsImplicitDefUse(MI, MO)) {
const unsigned Reg = MO.getReg();
PassthruRegs.insert(Reg);
}
void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx,
- const char *tag, const char *header,
+ const char *tag,
+ const char *header,
const char *footer) {
unsigned *KillIndices = State->GetKillIndices();
unsigned *DefIndices = State->GetDefIndices();
- std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
+ std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
RegRefs = State->GetRegRefs();
if (!State->IsLive(Reg)) {
RegRefs.erase(Reg);
State->LeaveGroup(Reg);
DEBUG(if (header != NULL) {
- errs() << header << TRI->getName(Reg); header = NULL; });
- DEBUG(errs() << "->g" << State->GetGroup(Reg) << tag);
+ dbgs() << header << TRI->getName(Reg); header = NULL; });
+ DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << tag);
}
// Repeat for subregisters.
for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
RegRefs.erase(SubregReg);
State->LeaveGroup(SubregReg);
DEBUG(if (header != NULL) {
- errs() << header << TRI->getName(Reg); header = NULL; });
- DEBUG(errs() << " " << TRI->getName(SubregReg) << "->g" <<
+ dbgs() << header << TRI->getName(Reg); header = NULL; });
+ DEBUG(dbgs() << " " << TRI->getName(SubregReg) << "->g" <<
State->GetGroup(SubregReg) << tag);
}
}
- DEBUG(if ((header == NULL) && (footer != NULL)) errs() << footer);
+ DEBUG(if ((header == NULL) && (footer != NULL)) dbgs() << footer);
}
-void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI, unsigned Count,
- std::set<unsigned>& PassthruRegs) {
+void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI,
+ unsigned Count,
+ std::set<unsigned>& PassthruRegs) {
unsigned *DefIndices = State->GetDefIndices();
- std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
+ std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
RegRefs = State->GetRegRefs();
// Handle dead defs by simulating a last-use of the register just
if (!MO.isReg() || !MO.isDef()) continue;
unsigned Reg = MO.getReg();
if (Reg == 0) continue;
-
+
HandleLastUse(Reg, Count + 1, "", "\tDead Def: ", "\n");
}
- DEBUG(errs() << "\tDef Groups:");
+ DEBUG(dbgs() << "\tDef Groups:");
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg() || !MO.isDef()) continue;
unsigned Reg = MO.getReg();
if (Reg == 0) continue;
- DEBUG(errs() << " " << TRI->getName(Reg) << "=g" << State->GetGroup(Reg));
+ DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" << State->GetGroup(Reg));
// If MI's defs have a special allocation requirement, don't allow
// any def registers to be changed. Also assume all registers
// defined in a call must not be changed (ABI).
if (MI->getDesc().isCall() || MI->getDesc().hasExtraDefRegAllocReq()) {
- DEBUG(if (State->GetGroup(Reg) != 0) errs() << "->g0(alloc-req)");
+ DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
State->UnionGroups(Reg, 0);
}
unsigned AliasReg = *Alias;
if (State->IsLive(AliasReg)) {
State->UnionGroups(Reg, AliasReg);
- DEBUG(errs() << "->g" << State->GetGroup(Reg) << "(via " <<
+ DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via " <<
TRI->getName(AliasReg) << ")");
}
}
-
+
// Note register reference...
const TargetRegisterClass *RC = NULL;
if (i < MI->getDesc().getNumOperands())
RegRefs.insert(std::make_pair(Reg, RR));
}
- DEBUG(errs() << '\n');
+ DEBUG(dbgs() << '\n');
// Scan the register defs for this instruction and update
// live-ranges.
unsigned Reg = MO.getReg();
if (Reg == 0) continue;
// Ignore KILLs and passthru registers for liveness...
- if ((MI->getOpcode() == TargetInstrInfo::KILL) ||
- (PassthruRegs.count(Reg) != 0))
+ if (MI->isKill() || (PassthruRegs.count(Reg) != 0))
continue;
// Update def for Reg and aliases.
}
void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr *MI,
- unsigned Count) {
- DEBUG(errs() << "\tUse Groups:");
- std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
+ unsigned Count) {
+ DEBUG(dbgs() << "\tUse Groups:");
+ std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
RegRefs = State->GetRegRefs();
// Scan the register uses for this instruction and update
if (!MO.isReg() || !MO.isUse()) continue;
unsigned Reg = MO.getReg();
if (Reg == 0) continue;
-
- DEBUG(errs() << " " << TRI->getName(Reg) << "=g" <<
- State->GetGroup(Reg));
+
+ DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" <<
+ State->GetGroup(Reg));
// It wasn't previously live but now it is, this is a kill. Forget
// the previous live-range information and start a new live-range
// any use registers to be changed. Also assume all registers
// used in a call must not be changed (ABI).
if (MI->getDesc().isCall() || MI->getDesc().hasExtraSrcRegAllocReq()) {
- DEBUG(if (State->GetGroup(Reg) != 0) errs() << "->g0(alloc-req)");
+ DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
State->UnionGroups(Reg, 0);
}
AggressiveAntiDepState::RegisterReference RR = { &MO, RC };
RegRefs.insert(std::make_pair(Reg, RR));
}
-
- DEBUG(errs() << '\n');
+
+ DEBUG(dbgs() << '\n');
// Form a group of all defs and uses of a KILL instruction to ensure
// that all registers are renamed as a group.
- if (MI->getOpcode() == TargetInstrInfo::KILL) {
- DEBUG(errs() << "\tKill Group:");
+ if (MI->isKill()) {
+ DEBUG(dbgs() << "\tKill Group:");
unsigned FirstReg = 0;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
if (!MO.isReg()) continue;
unsigned Reg = MO.getReg();
if (Reg == 0) continue;
-
+
if (FirstReg != 0) {
- DEBUG(errs() << "=" << TRI->getName(Reg));
+ DEBUG(dbgs() << "=" << TRI->getName(Reg));
State->UnionGroups(FirstReg, Reg);
} else {
- DEBUG(errs() << " " << TRI->getName(Reg));
+ DEBUG(dbgs() << " " << TRI->getName(Reg));
FirstReg = Reg;
}
}
-
- DEBUG(errs() << "->g" << State->GetGroup(FirstReg) << '\n');
+
+ DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n');
}
}
// Check all references that need rewriting for Reg. For each, use
// the corresponding register class to narrow the set of registers
// that are appropriate for renaming.
- std::pair<std::multimap<unsigned,
+ std::pair<std::multimap<unsigned,
AggressiveAntiDepState::RegisterReference>::iterator,
std::multimap<unsigned,
AggressiveAntiDepState::RegisterReference>::iterator>
Range = State->GetRegRefs().equal_range(Reg);
- for (std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>::iterator
- Q = Range.first, QE = Range.second; Q != QE; ++Q) {
+ for (std::multimap<unsigned,
+ AggressiveAntiDepState::RegisterReference>::iterator Q = Range.first,
+ QE = Range.second; Q != QE; ++Q) {
const TargetRegisterClass *RC = Q->second.RC;
if (RC == NULL) continue;
BV &= RCBV;
}
- DEBUG(errs() << " " << RC->getName());
+ DEBUG(dbgs() << " " << RC->getName());
}
-
+
return BV;
-}
+}
bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
unsigned AntiDepGroupIndex,
std::map<unsigned, unsigned> &RenameMap) {
unsigned *KillIndices = State->GetKillIndices();
unsigned *DefIndices = State->GetDefIndices();
- std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
+ std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
RegRefs = State->GetRegRefs();
// Collect all referenced registers in the same group as
// Find the "superest" register in the group. At the same time,
// collect the BitVector of registers that can be used to rename
// each register.
- DEBUG(errs() << "\tRename Candidates for Group g" << AntiDepGroupIndex << ":\n");
+ DEBUG(dbgs() << "\tRename Candidates for Group g" << AntiDepGroupIndex
+ << ":\n");
std::map<unsigned, BitVector> RenameRegisterMap;
unsigned SuperReg = 0;
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
// If Reg has any references, then collect possible rename regs
if (RegRefs.count(Reg) > 0) {
- DEBUG(errs() << "\t\t" << TRI->getName(Reg) << ":");
-
+ DEBUG(dbgs() << "\t\t" << TRI->getName(Reg) << ":");
+
BitVector BV = GetRenameRegisters(Reg);
RenameRegisterMap.insert(std::pair<unsigned, BitVector>(Reg, BV));
- DEBUG(errs() << " ::");
+ DEBUG(dbgs() << " ::");
DEBUG(for (int r = BV.find_first(); r != -1; r = BV.find_next(r))
- errs() << " " << TRI->getName(r));
- DEBUG(errs() << "\n");
+ dbgs() << " " << TRI->getName(r));
+ DEBUG(dbgs() << "\n");
}
}
static int renamecnt = 0;
if (renamecnt++ % DebugDiv != DebugMod)
return false;
-
- errs() << "*** Performing rename " << TRI->getName(SuperReg) <<
+
+ dbgs() << "*** Performing rename " << TRI->getName(SuperReg) <<
" for debug ***\n";
}
#endif
// order. If that register is available, and the corresponding
// registers are available for the other group subregisters, then we
// can use those registers to rename.
- const TargetRegisterClass *SuperRC =
+ const TargetRegisterClass *SuperRC =
TRI->getPhysicalRegisterRegClass(SuperReg, MVT::Other);
-
+
const TargetRegisterClass::iterator RB = SuperRC->allocation_order_begin(MF);
const TargetRegisterClass::iterator RE = SuperRC->allocation_order_end(MF);
if (RB == RE) {
- DEBUG(errs() << "\tEmpty Super Regclass!!\n");
+ DEBUG(dbgs() << "\tEmpty Super Regclass!!\n");
return false;
}
- DEBUG(errs() << "\tFind Registers:");
+ DEBUG(dbgs() << "\tFind Registers:");
if (RenameOrder.count(SuperRC) == 0)
RenameOrder.insert(RenameOrderType::value_type(SuperRC, RE));
const unsigned NewSuperReg = *R;
// Don't replace a register with itself.
if (NewSuperReg == SuperReg) continue;
-
- DEBUG(errs() << " [" << TRI->getName(NewSuperReg) << ':');
+
+ DEBUG(dbgs() << " [" << TRI->getName(NewSuperReg) << ':');
RenameMap.clear();
// For each referenced group register (which must be a SuperReg or
NewReg = TRI->getSubReg(NewSuperReg, NewSubRegIdx);
}
- DEBUG(errs() << " " << TRI->getName(NewReg));
-
+ DEBUG(dbgs() << " " << TRI->getName(NewReg));
+
// Check if Reg can be renamed to NewReg.
BitVector BV = RenameRegisterMap[Reg];
if (!BV.test(NewReg)) {
- DEBUG(errs() << "(no rename)");
+ DEBUG(dbgs() << "(no rename)");
goto next_super_reg;
}
// must also check all aliases of NewReg, because we can't define a
// register when any sub or super is already live.
if (State->IsLive(NewReg) || (KillIndices[Reg] > DefIndices[NewReg])) {
- DEBUG(errs() << "(live)");
+ DEBUG(dbgs() << "(live)");
goto next_super_reg;
} else {
bool found = false;
for (const unsigned *Alias = TRI->getAliasSet(NewReg);
*Alias; ++Alias) {
unsigned AliasReg = *Alias;
- if (State->IsLive(AliasReg) || (KillIndices[Reg] > DefIndices[AliasReg])) {
- DEBUG(errs() << "(alias " << TRI->getName(AliasReg) << " live)");
+ if (State->IsLive(AliasReg) ||
+ (KillIndices[Reg] > DefIndices[AliasReg])) {
+ DEBUG(dbgs() << "(alias " << TRI->getName(AliasReg) << " live)");
found = true;
break;
}
if (found)
goto next_super_reg;
}
-
+
// Record that 'Reg' can be renamed to 'NewReg'.
RenameMap.insert(std::pair<unsigned, unsigned>(Reg, NewReg));
}
-
+
// If we fall-out here, then every register in the group can be
// renamed, as recorded in RenameMap.
RenameOrder.erase(SuperRC);
RenameOrder.insert(RenameOrderType::value_type(SuperRC, R));
- DEBUG(errs() << "]\n");
+ DEBUG(dbgs() << "]\n");
return true;
next_super_reg:
- DEBUG(errs() << ']');
+ DEBUG(dbgs() << ']');
} while (R != EndR);
- DEBUG(errs() << '\n');
+ DEBUG(dbgs() << '\n');
// No registers are free and available!
return false;
unsigned InsertPosIndex) {
unsigned *KillIndices = State->GetKillIndices();
unsigned *DefIndices = State->GetDefIndices();
- std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
+ std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
RegRefs = State->GetRegRefs();
// The code below assumes that there is at least one instruction,
// so just duck out immediately if the block is empty.
if (SUnits.empty()) return 0;
-
+
// For each regclass the next register to use for renaming.
RenameOrderType RenameOrder;
if (CriticalPathSet.any()) {
for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
SUnit *SU = &SUnits[i];
- if (!CriticalPathSU ||
- ((SU->getDepth() + SU->Latency) >
+ if (!CriticalPathSU ||
+ ((SU->getDepth() + SU->Latency) >
(CriticalPathSU->getDepth() + CriticalPathSU->Latency))) {
CriticalPathSU = SU;
}
}
-
+
CriticalPathMI = CriticalPathSU->getInstr();
}
-#ifndef NDEBUG
- DEBUG(errs() << "\n===== Aggressive anti-dependency breaking\n");
- DEBUG(errs() << "Available regs:");
+#ifndef NDEBUG
+ DEBUG(dbgs() << "\n===== Aggressive anti-dependency breaking\n");
+ DEBUG(dbgs() << "Available regs:");
for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
if (!State->IsLive(Reg))
- DEBUG(errs() << " " << TRI->getName(Reg));
+ DEBUG(dbgs() << " " << TRI->getName(Reg));
}
- DEBUG(errs() << '\n');
+ DEBUG(dbgs() << '\n');
#endif
// Attempt to break anti-dependence edges. Walk the instructions
I != E; --Count) {
MachineInstr *MI = --I;
- DEBUG(errs() << "Anti: ");
+ DEBUG(dbgs() << "Anti: ");
DEBUG(MI->dump());
std::set<unsigned> PassthruRegs;
// Process the defs in MI...
PrescanInstruction(MI, Count, PassthruRegs);
-
+
// The dependence edges that represent anti- and output-
// dependencies that are candidates for breaking.
std::vector<SDep*> Edges;
if (MI == CriticalPathMI) {
CriticalPathSU = CriticalPathStep(CriticalPathSU);
CriticalPathMI = (CriticalPathSU) ? CriticalPathSU->getInstr() : 0;
- } else {
+ } else {
ExcludeRegs = &CriticalPathSet;
}
// Ignore KILL instructions (they form a group in ScanInstruction
// but don't cause any anti-dependence breaking themselves)
- if (MI->getOpcode() != TargetInstrInfo::KILL) {
+ if (!MI->isKill()) {
// Attempt to break each anti-dependency...
for (unsigned i = 0, e = Edges.size(); i != e; ++i) {
SDep *Edge = Edges[i];
SUnit *NextSU = Edge->getSUnit();
-
+
if ((Edge->getKind() != SDep::Anti) &&
(Edge->getKind() != SDep::Output)) continue;
-
+
unsigned AntiDepReg = Edge->getReg();
- DEBUG(errs() << "\tAntidep reg: " << TRI->getName(AntiDepReg));
+ DEBUG(dbgs() << "\tAntidep reg: " << TRI->getName(AntiDepReg));
assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
-
+
if (!AllocatableSet.test(AntiDepReg)) {
// Don't break anti-dependencies on non-allocatable registers.
- DEBUG(errs() << " (non-allocatable)\n");
+ DEBUG(dbgs() << " (non-allocatable)\n");
continue;
} else if ((ExcludeRegs != NULL) && ExcludeRegs->test(AntiDepReg)) {
// Don't break anti-dependencies for critical path registers
// if not on the critical path
- DEBUG(errs() << " (not critical-path)\n");
+ DEBUG(dbgs() << " (not critical-path)\n");
continue;
} else if (PassthruRegs.count(AntiDepReg) != 0) {
// If the anti-dep register liveness "passes-thru", then
// don't try to change it. It will be changed along with
// the use if required to break an earlier antidep.
- DEBUG(errs() << " (passthru)\n");
+ DEBUG(dbgs() << " (passthru)\n");
continue;
} else {
// No anti-dep breaking for implicit deps
MachineOperand *AntiDepOp = MI->findRegisterDefOperand(AntiDepReg);
- assert(AntiDepOp != NULL && "Can't find index for defined register operand");
+ assert(AntiDepOp != NULL &&
+ "Can't find index for defined register operand");
if ((AntiDepOp == NULL) || AntiDepOp->isImplicit()) {
- DEBUG(errs() << " (implicit)\n");
+ DEBUG(dbgs() << " (implicit)\n");
continue;
}
-
+
// If the SUnit has other dependencies on the SUnit that
// it anti-depends on, don't bother breaking the
// anti-dependency since those edges would prevent such
PE = PathSU->Preds.end(); P != PE; ++P) {
if ((P->getSUnit() == NextSU) && (P->getKind() != SDep::Anti) &&
(P->getKind() != SDep::Output)) {
- DEBUG(errs() << " (real dependency)\n");
+ DEBUG(dbgs() << " (real dependency)\n");
AntiDepReg = 0;
break;
- } else if ((P->getSUnit() != NextSU) &&
- (P->getKind() == SDep::Data) &&
+ } else if ((P->getSUnit() != NextSU) &&
+ (P->getKind() == SDep::Data) &&
(P->getReg() == AntiDepReg)) {
- DEBUG(errs() << " (other dependency)\n");
+ DEBUG(dbgs() << " (other dependency)\n");
AntiDepReg = 0;
break;
}
}
-
+
if (AntiDepReg == 0) continue;
}
-
+
assert(AntiDepReg != 0);
if (AntiDepReg == 0) continue;
-
+
// Determine AntiDepReg's register group.
const unsigned GroupIndex = State->GetGroup(AntiDepReg);
if (GroupIndex == 0) {
- DEBUG(errs() << " (zero group)\n");
+ DEBUG(dbgs() << " (zero group)\n");
continue;
}
-
- DEBUG(errs() << '\n');
-
+
+ DEBUG(dbgs() << '\n');
+
// Look for a suitable register to use to break the anti-dependence.
std::map<unsigned, unsigned> RenameMap;
if (FindSuitableFreeRegisters(GroupIndex, RenameOrder, RenameMap)) {
- DEBUG(errs() << "\tBreaking anti-dependence edge on "
+ DEBUG(dbgs() << "\tBreaking anti-dependence edge on "
<< TRI->getName(AntiDepReg) << ":");
-
+
// Handle each group register...
for (std::map<unsigned, unsigned>::iterator
S = RenameMap.begin(), E = RenameMap.end(); S != E; ++S) {
unsigned CurrReg = S->first;
unsigned NewReg = S->second;
-
- DEBUG(errs() << " " << TRI->getName(CurrReg) << "->" <<
- TRI->getName(NewReg) << "(" <<
+
+ DEBUG(dbgs() << " " << TRI->getName(CurrReg) << "->" <<
+ TRI->getName(NewReg) << "(" <<
RegRefs.count(CurrReg) << " refs)");
-
+
// Update the references to the old register CurrReg to
// refer to the new register NewReg.
- std::pair<std::multimap<unsigned,
- AggressiveAntiDepState::RegisterReference>::iterator,
+ std::pair<std::multimap<unsigned,
+ AggressiveAntiDepState::RegisterReference>::iterator,
std::multimap<unsigned,
- AggressiveAntiDepState::RegisterReference>::iterator>
+ AggressiveAntiDepState::RegisterReference>::iterator>
Range = RegRefs.equal_range(CurrReg);
- for (std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>::iterator
+ for (std::multimap<unsigned,
+ AggressiveAntiDepState::RegisterReference>::iterator
Q = Range.first, QE = Range.second; Q != QE; ++Q) {
Q->second.Operand->setReg(NewReg);
}
-
+
// We just went back in time and modified history; the
// liveness information for CurrReg is now inconsistent. Set
// the state as if it were dead.
RegRefs.erase(NewReg);
DefIndices[NewReg] = DefIndices[CurrReg];
KillIndices[NewReg] = KillIndices[CurrReg];
-
+
State->UnionGroups(CurrReg, 0);
RegRefs.erase(CurrReg);
DefIndices[CurrReg] = KillIndices[CurrReg];
(DefIndices[CurrReg] == ~0u)) &&
"Kill and Def maps aren't consistent for AntiDepReg!");
}
-
+
++Broken;
- DEBUG(errs() << '\n');
+ DEBUG(dbgs() << '\n');
}
}
}
ScanInstruction(MI, Count);
}
-
+
return Broken;
}
projects / oota-llvm.git / blobdiff