//
//===----------------------------------------------------------------------===//
-#define DEBUG_TYPE "asm-printer"
+#include "ByteStreamer.h"
#include "llvm/CodeGen/AsmPrinter.h"
#include "llvm/ADT/SmallBitVector.h"
#include "llvm/ADT/Twine.h"
#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
+#define DEBUG_TYPE "asm-printer"
+
//===----------------------------------------------------------------------===//
// Dwarf Emission Helper Routines
//===----------------------------------------------------------------------===//
default:
llvm_unreachable("Invalid encoded value.");
case dwarf::DW_EH_PE_absptr:
- return TM.getDataLayout()->getPointerSize();
+ return TM.getSubtargetImpl()->getDataLayout()->getPointerSize();
case dwarf::DW_EH_PE_udata2:
return 2;
case dwarf::DW_EH_PE_udata4:
EmitLabelDifference(Label, SectionLabel, 4);
}
-
/// Emit a dwarf register operation.
-static void emitDwarfRegOp(const AsmPrinter &AP, int Reg) {
+static void emitDwarfRegOp(ByteStreamer &Streamer, int Reg) {
assert(Reg >= 0);
if (Reg < 32) {
- AP.OutStreamer.AddComment(
- dwarf::OperationEncodingString(dwarf::DW_OP_reg0 + Reg));
- AP.EmitInt8(dwarf::DW_OP_reg0 + Reg);
+ Streamer.EmitInt8(dwarf::DW_OP_reg0 + Reg,
+ dwarf::OperationEncodingString(dwarf::DW_OP_reg0 + Reg));
} else {
- AP.OutStreamer.AddComment("DW_OP_regx");
- AP.EmitInt8(dwarf::DW_OP_regx);
- AP.OutStreamer.AddComment(Twine(Reg));
- AP.EmitULEB128(Reg);
+ Streamer.EmitInt8(dwarf::DW_OP_regx, "DW_OP_regx");
+ Streamer.EmitULEB128(Reg, Twine(Reg));
}
}
/// Emit an (double-)indirect dwarf register operation.
-static void emitDwarfRegOpIndirect(const AsmPrinter &AP,
- int Reg, int Offset, bool Deref) {
+static void emitDwarfRegOpIndirect(ByteStreamer &Streamer, int Reg, int Offset,
+ bool Deref) {
assert(Reg >= 0);
if (Reg < 32) {
- AP.OutStreamer.AddComment(
- dwarf::OperationEncodingString(dwarf::DW_OP_breg0 + Reg));
- AP.EmitInt8(dwarf::DW_OP_breg0 + Reg);
+ Streamer.EmitInt8(dwarf::DW_OP_breg0 + Reg,
+ dwarf::OperationEncodingString(dwarf::DW_OP_breg0 + Reg));
} else {
- AP.OutStreamer.AddComment("DW_OP_bregx");
- AP.EmitInt8(dwarf::DW_OP_bregx);
- AP.OutStreamer.AddComment(Twine(Reg));
- AP.EmitULEB128(Reg);
+ Streamer.EmitInt8(dwarf::DW_OP_bregx, "DW_OP_bregx");
+ Streamer.EmitULEB128(Reg, Twine(Reg));
}
- AP.EmitSLEB128(Offset);
+ Streamer.EmitSLEB128(Offset);
if (Deref)
- AP.EmitInt8(dwarf::DW_OP_deref);
+ Streamer.EmitInt8(dwarf::DW_OP_deref, "DW_OP_deref");
}
-/// Emit a dwarf register operation for describing
-/// - a small value occupying only part of a register or
-/// - a small register representing only part of a value.
-static void emitDwarfOpPiece(const AsmPrinter &AP,
- unsigned Size, unsigned Offset) {
- assert(Size > 0);
- if (Offset > 0) {
- AP.OutStreamer.AddComment("DW_OP_bit_piece");
- AP.EmitInt8(dwarf::DW_OP_bit_piece);
- AP.OutStreamer.AddComment(Twine(Size));
- AP.EmitULEB128(Size);
- AP.OutStreamer.AddComment(Twine(Offset));
- AP.EmitULEB128(Offset);
+void AsmPrinter::EmitDwarfOpPiece(ByteStreamer &Streamer, unsigned SizeInBits,
+ unsigned OffsetInBits) const {
+ assert(SizeInBits > 0 && "piece has size zero");
+ const unsigned SizeOfByte = 8;
+ if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
+ Streamer.EmitInt8(dwarf::DW_OP_bit_piece, "DW_OP_bit_piece");
+ Streamer.EmitULEB128(SizeInBits, Twine(SizeInBits));
+ Streamer.EmitULEB128(OffsetInBits, Twine(OffsetInBits));
} else {
- AP.OutStreamer.AddComment("DW_OP_piece");
- AP.EmitInt8(dwarf::DW_OP_piece);
- unsigned ByteSize = Size / 8; // Assuming 8 bits per byte.
- AP.OutStreamer.AddComment(Twine(ByteSize));
- AP.EmitULEB128(ByteSize);
+ Streamer.EmitInt8(dwarf::DW_OP_piece, "DW_OP_piece");
+ unsigned ByteSize = SizeInBits / SizeOfByte;
+ Streamer.EmitULEB128(ByteSize, Twine(ByteSize));
}
}
-/// Some targets do not provide a DWARF register number for every
-/// register. This function attempts to emit a dwarf register by
-/// emitting a piece of a super-register or by piecing together
-/// multiple subregisters that alias the register.
-static void EmitDwarfRegOpPiece(const AsmPrinter &AP,
- const MachineLocation &MLoc) {
- assert(!MLoc.isIndirect());
- const TargetRegisterInfo *TRI = AP.TM.getRegisterInfo();
+/// Emit a shift-right dwarf expression.
+static void emitDwarfOpShr(ByteStreamer &Streamer,
+ unsigned ShiftBy) {
+ Streamer.EmitInt8(dwarf::DW_OP_constu, "DW_OP_constu");
+ Streamer.EmitULEB128(ShiftBy);
+ Streamer.EmitInt8(dwarf::DW_OP_shr, "DW_OP_shr");
+}
+
+// Some targets do not provide a DWARF register number for every
+// register. This function attempts to emit a DWARF register by
+// emitting a piece of a super-register or by piecing together
+// multiple subregisters that alias the register.
+void AsmPrinter::EmitDwarfRegOpPiece(ByteStreamer &Streamer,
+ const MachineLocation &MLoc,
+ unsigned PieceSizeInBits,
+ unsigned PieceOffsetInBits) const {
+ assert(MLoc.isReg() && "MLoc must be a register");
+ const TargetRegisterInfo *TRI = TM.getSubtargetImpl()->getRegisterInfo();
int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false);
+ // If this is a valid register number, emit it.
+ if (Reg >= 0) {
+ emitDwarfRegOp(Streamer, Reg);
+ EmitDwarfOpPiece(Streamer, PieceSizeInBits, PieceOffsetInBits);
+ return;
+ }
+
// Walk up the super-register chain until we find a valid number.
// For example, EAX on x86_64 is a 32-bit piece of RAX with offset 0.
for (MCSuperRegIterator SR(MLoc.getReg(), TRI); SR.isValid(); ++SR) {
if (Reg >= 0) {
unsigned Idx = TRI->getSubRegIndex(*SR, MLoc.getReg());
unsigned Size = TRI->getSubRegIdxSize(Idx);
- unsigned Offset = TRI->getSubRegIdxOffset(Idx);
- AP.OutStreamer.AddComment("super-register");
- emitDwarfRegOp(AP, Reg);
- emitDwarfOpPiece(AP, Size, Offset);
+ unsigned RegOffset = TRI->getSubRegIdxOffset(Idx);
+ OutStreamer.AddComment("super-register");
+ emitDwarfRegOp(Streamer, Reg);
+ if (PieceOffsetInBits == RegOffset) {
+ EmitDwarfOpPiece(Streamer, Size, RegOffset);
+ } else {
+ // If this is part of a variable in a sub-register at a
+ // non-zero offset, we need to manually shift the value into
+ // place, since the DW_OP_piece describes the part of the
+ // variable, not the position of the subregister.
+ if (RegOffset)
+ emitDwarfOpShr(Streamer, RegOffset);
+ EmitDwarfOpPiece(Streamer, Size, PieceOffsetInBits);
+ }
return;
}
}
//
// Keep track of the current position so we can emit the more
// efficient DW_OP_piece.
- unsigned CurPos = 0;
+ unsigned CurPos = PieceOffsetInBits;
// The size of the register in bits, assuming 8 bits per byte.
- unsigned RegSize = TRI->getMinimalPhysRegClass(MLoc.getReg())->getSize()*8;
+ unsigned RegSize = TRI->getMinimalPhysRegClass(MLoc.getReg())->getSize() * 8;
// Keep track of the bits in the register we already emitted, so we
// can avoid emitting redundant aliasing subregs.
SmallBitVector Coverage(RegSize, false);
// Intersection between the bits we already emitted and the bits
// covered by this subregister.
SmallBitVector Intersection(RegSize, false);
- Intersection.set(Offset, Offset+Size);
+ Intersection.set(Offset, Offset + Size);
Intersection ^= Coverage;
// If this sub-register has a DWARF number and we haven't covered
// its range, emit a DWARF piece for it.
if (Reg >= 0 && Intersection.any()) {
- AP.OutStreamer.AddComment("sub-register");
- emitDwarfRegOp(AP, Reg);
- emitDwarfOpPiece(AP, Size, Offset == CurPos ? 0 : Offset);
- CurPos = Offset+Size;
+ OutStreamer.AddComment("sub-register");
+ emitDwarfRegOp(Streamer, Reg);
+ EmitDwarfOpPiece(Streamer, Size, Offset == CurPos ? 0 : Offset);
+ CurPos = Offset + Size;
// Mark it as emitted.
- Coverage.set(Offset, Offset+Size);
+ Coverage.set(Offset, Offset + Size);
}
}
- if (CurPos == 0) {
+ if (CurPos == PieceOffsetInBits) {
// FIXME: We have no reasonable way of handling errors in here.
- AP.OutStreamer.AddComment("nop (could not find a dwarf register number)");
- AP.EmitInt8(dwarf::DW_OP_nop);
+ Streamer.EmitInt8(dwarf::DW_OP_nop,
+ "nop (could not find a dwarf register number)");
}
}
/// EmitDwarfRegOp - Emit dwarf register operation.
-void AsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc,
+void AsmPrinter::EmitDwarfRegOp(ByteStreamer &Streamer,
+ const MachineLocation &MLoc,
bool Indirect) const {
- const TargetRegisterInfo *TRI = TM.getRegisterInfo();
+ const TargetRegisterInfo *TRI = TM.getSubtargetImpl()->getRegisterInfo();
int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false);
if (Reg < 0) {
// We assume that pointers are always in an addressable register.
// caller might be in the middle of a dwarf expression. We should
// probably assert that Reg >= 0 once debug info generation is more
// mature.
- OutStreamer.AddComment(
- "nop (invalid dwarf register number for indirect loc)");
- EmitInt8(dwarf::DW_OP_nop);
+ Streamer.EmitInt8(dwarf::DW_OP_nop,
+ "nop (invalid dwarf register number for indirect loc)");
return;
}
// Attempt to find a valid super- or sub-register.
- if (!Indirect && !MLoc.isIndirect())
- return EmitDwarfRegOpPiece(*this, MLoc);
+ return EmitDwarfRegOpPiece(Streamer, MLoc);
}
if (MLoc.isIndirect())
- emitDwarfRegOpIndirect(*this, Reg, MLoc.getOffset(), Indirect);
+ emitDwarfRegOpIndirect(Streamer, Reg, MLoc.getOffset(), Indirect);
else if (Indirect)
- emitDwarfRegOpIndirect(*this, Reg, 0, false);
+ emitDwarfRegOpIndirect(Streamer, Reg, 0, false);
else
- emitDwarfRegOp(*this, Reg);
+ emitDwarfRegOp(Streamer, Reg);
}
//===----------------------------------------------------------------------===//
case MCCFIInstruction::OpWindowSave:
OutStreamer.EmitCFIWindowSave();
break;
+ case MCCFIInstruction::OpSameValue:
+ OutStreamer.EmitCFISameValue(Inst.getRegister());
+ break;
}
}
projects / oota-llvm.git / blobdiff