//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
+#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h"
#include <algorithm>
cl::desc("Max number of predecessors to consider tail merging"),
cl::init(100), cl::Hidden);
- struct BranchFolder : public MachineFunctionPass {
+ struct VISIBILITY_HIDDEN BranchFolder : public MachineFunctionPass {
static char ID;
- BranchFolder(bool defaultEnableTailMerge) :
+ explicit BranchFolder(bool defaultEnableTailMerge) :
MachineFunctionPass((intptr_t)&ID) {
switch (FlagEnableTailMerge) {
case cl::BOU_UNSET: EnableTailMerge = defaultEnableTailMerge; break;
MachineBasicBlock::iterator BBI1);
std::vector<std::pair<unsigned,MachineBasicBlock*> > MergePotentials;
- const MRegisterInfo *RegInfo;
+ const TargetRegisterInfo *RegInfo;
RegScavenger *RS;
// Branch optzn.
bool OptimizeBranches(MachineFunction &MF);
void OptimizeBlock(MachineBasicBlock *MBB);
void RemoveDeadBlock(MachineBasicBlock *MBB);
+ bool OptimizeImpDefsBlock(MachineBasicBlock *MBB);
bool CanFallThrough(MachineBasicBlock *CurBB);
bool CanFallThrough(MachineBasicBlock *CurBB, bool BranchUnAnalyzable,
MF->getBasicBlockList().erase(MBB);
}
+/// OptimizeImpDefsBlock - If a basic block is just a bunch of implicit_def
+/// followed by terminators, and if the implicitly defined registers are not
+/// used by the terminators, remove those implicit_def's. e.g.
+/// BB1:
+/// r0 = implicit_def
+/// r1 = implicit_def
+/// br
+/// This block can be optimized away later if the implicit instructions are
+/// removed.
+bool BranchFolder::OptimizeImpDefsBlock(MachineBasicBlock *MBB) {
+ SmallSet<unsigned, 4> ImpDefRegs;
+ MachineBasicBlock::iterator I = MBB->begin();
+ while (I != MBB->end()) {
+ if (I->getOpcode() != TargetInstrInfo::IMPLICIT_DEF)
+ break;
+ unsigned Reg = I->getOperand(0).getReg();
+ ImpDefRegs.insert(Reg);
+ for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
+ unsigned SubReg = *SubRegs; ++SubRegs)
+ ImpDefRegs.insert(SubReg);
+ ++I;
+ }
+ if (ImpDefRegs.empty())
+ return false;
+
+ MachineBasicBlock::iterator FirstTerm = I;
+ while (I != MBB->end()) {
+ if (!TII->isUnpredicatedTerminator(I))
+ return false;
+ // See if it uses any of the implicitly defined registers.
+ for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = I->getOperand(i);
+ if (!MO.isReg() || !MO.isUse())
+ continue;
+ unsigned Reg = MO.getReg();
+ if (ImpDefRegs.count(Reg))
+ return false;
+ }
+ ++I;
+ }
+
+ I = MBB->begin();
+ while (I != FirstTerm) {
+ MachineInstr *ImpDefMI = &*I;
+ ++I;
+ MBB->erase(ImpDefMI);
+ }
+
+ return true;
+}
+
bool BranchFolder::runOnMachineFunction(MachineFunction &MF) {
TII = MF.getTarget().getInstrInfo();
if (!TII) return false;
+ RegInfo = MF.getTarget().getRegisterInfo();
+
// Fix CFG. The later algorithms expect it to be right.
bool EverMadeChange = false;
for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; I++) {
std::vector<MachineOperand> Cond;
if (!TII->AnalyzeBranch(*MBB, TBB, FBB, Cond))
EverMadeChange |= MBB->CorrectExtraCFGEdges(TBB, FBB, !Cond.empty());
+ EverMadeChange |= OptimizeImpDefsBlock(MBB);
}
- RegInfo = MF.getTarget().getRegisterInfo();
RS = RegInfo->requiresRegisterScavenging(MF) ? new RegScavenger() : NULL;
MMI = getAnalysisToUpdate<MachineModuleInfo>();
for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) {
MachineOperand &Op = I->getOperand(op);
if (!Op.isJumpTableIndex()) continue;
- unsigned NewIdx = JTMapping[Op.getJumpTableIndex()];
- Op.setJumpTableIndex(NewIdx);
+ unsigned NewIdx = JTMapping[Op.getIndex()];
+ Op.setIndex(NewIdx);
// Remember that this JT is live.
JTIsLive[NewIdx] = true;
case MachineOperand::MO_Register: OperandHash = Op.getReg(); break;
case MachineOperand::MO_Immediate: OperandHash = Op.getImm(); break;
case MachineOperand::MO_MachineBasicBlock:
- OperandHash = Op.getMachineBasicBlock()->getNumber();
+ OperandHash = Op.getMBB()->getNumber();
break;
- case MachineOperand::MO_FrameIndex: OperandHash = Op.getFrameIndex(); break;
+ case MachineOperand::MO_FrameIndex:
case MachineOperand::MO_ConstantPoolIndex:
- OperandHash = Op.getConstantPoolIndex();
- break;
case MachineOperand::MO_JumpTableIndex:
- OperandHash = Op.getJumpTableIndex();
+ OperandHash = Op.getIndex();
break;
case MachineOperand::MO_GlobalAddress:
case MachineOperand::MO_ExternalSymbol:
unsigned TailLen = 0;
while (I1 != MBB1->begin() && I2 != MBB2->begin()) {
--I1; --I2;
- if (!I1->isIdenticalTo(I2)) {
+ if (!I1->isIdenticalTo(I2) ||
+ // FIXME: This check is dubious. It's used to get around a problem where
+ // people incorrectly expect inline asm directives to remain in the same
+ // relative order. This is untenable because normal compiler
+ // optimizations (like this one) may reorder and/or merge these
+ // directives.
+ I1->getOpcode() == TargetInstrInfo::INLINEASM) {
++I1; ++I2;
break;
}
/// EstimateRuntime - Make a rough estimate for how long it will take to run
/// the specified code.
static unsigned EstimateRuntime(MachineBasicBlock::iterator I,
- MachineBasicBlock::iterator E,
- const TargetInstrInfo *TII) {
+ MachineBasicBlock::iterator E) {
unsigned Time = 0;
for (; I != E; ++I) {
- const TargetInstrDescriptor &TID = TII->get(I->getOpcode());
- if (TID.Flags & M_CALL_FLAG)
+ const TargetInstrDesc &TID = I->getDesc();
+ if (TID.isCall())
Time += 10;
- else if (TID.Flags & (M_LOAD_FLAG|M_STORE_FLAG))
+ else if (TID.isSimpleLoad() || TID.mayStore())
Time += 2;
else
++Time;
MachineBasicBlock::iterator MBB1I,
MachineBasicBlock *MBB2,
MachineBasicBlock::iterator MBB2I,
- const TargetInstrInfo *TII,
MachineBasicBlock *PredBB) {
// If one block is the entry block, split the other one; we can't generate
// a branch to the entry block, as its label is not emitted.
// TODO: if we had some notion of which block was hotter, we could split
// the hot block, so it is the fall-through. Since we don't have profile info
// make a decision based on which will hurt most to split.
- unsigned MBB1Time = EstimateRuntime(MBB1->begin(), MBB1I, TII);
- unsigned MBB2Time = EstimateRuntime(MBB2->begin(), MBB2I, TII);
+ unsigned MBB1Time = EstimateRuntime(MBB1->begin(), MBB1I);
+ unsigned MBB2Time = EstimateRuntime(MBB2->begin(), MBB2I);
// If the MBB1 prefix takes "less time" to run than the MBB2 prefix, split the
// MBB1 block so it falls through. This will penalize the MBB2 path, but will
return true;
else if (p.second->getNumber() > q.second->getNumber())
return false;
- else
+ else {
+ // _GLIBCXX_DEBUG checks strict weak ordering, which involves comparing
+ // an object with itself.
+#ifndef _GLIBCXX_DEBUG
assert(0 && "Predecessor appears twice");
+#endif
+ return(false);
+ }
}
// See if any of the blocks in MergePotentials (which all have a common single
bool BranchFolder::TryMergeBlocks(MachineBasicBlock *SuccBB,
MachineBasicBlock* PredBB) {
- unsigned minCommonTailLength = (SuccBB ? 1 : 2);
+ // It doesn't make sense to save a single instruction since tail merging
+ // will add a jump.
+ // FIXME: Ask the target to provide the threshold?
+ unsigned minCommonTailLength = (SuccBB ? 1 : 2) + 1;
MadeChange = false;
// Sort by hash value so that blocks with identical end sequences sort
// Look through all the pairs of blocks that have the same hash as this
// one, and find the pair that has the largest number of instructions in
// common.
- // Since instructions may get combined later (e.g. single stores into
+ // Since instructions may get combined later (e.g. single stores into
// store multiple) this measure is not particularly accurate.
- MachineBasicBlock::iterator BBI1, BBI2;
+ MachineBasicBlock::iterator BBI1, BBI2;
unsigned FoundI = ~0U, FoundJ = ~0U;
unsigned maxCommonTailLength = 0U;
continue;
}
+ MachineBasicBlock::iterator TrialBBI1, TrialBBI2;
+ unsigned CommonTailLen = ComputeCommonTailLength(CurMBB, MBB2,
+ TrialBBI1, TrialBBI2);
+ if (CommonTailLen < minCommonTailLength)
+ continue;
+
// Decide whether we want to split CurMBB or MBB2.
- if (ShouldSplitFirstBlock(CurMBB, BBI1, MBB2, BBI2, TII, PredBB)) {
+ if (ShouldSplitFirstBlock(CurMBB, BBI1, MBB2, BBI2, PredBB)) {
CurMBB = SplitMBBAt(*CurMBB, BBI1);
BBI1 = CurMBB->begin();
MergePotentials.back().second = CurMBB;
} else if (FBB) {
if (TBB!=IBB && FBB!=IBB) // cbr then ubr
continue;
- } else if (Cond.size() == 0) {
+ } else if (Cond.empty()) {
if (TBB!=IBB) // ubr
continue;
} else {
/// a strict ordering, returning true for both (MBB1,MBB2) and (MBB2,MBB1) will
/// result in infinite loops.
static bool IsBetterFallthrough(MachineBasicBlock *MBB1,
- MachineBasicBlock *MBB2,
- const TargetInstrInfo &TII) {
+ MachineBasicBlock *MBB2) {
// Right now, we use a simple heuristic. If MBB2 ends with a call, and
// MBB1 doesn't, we prefer to fall through into MBB1. This allows us to
// optimize branches that branch to either a return block or an assert block
// into a fallthrough to the return.
if (MBB1->empty() || MBB2->empty()) return false;
+
+ // If there is a clear successor ordering we make sure that one block
+ // will fall through to the next
+ if (MBB1->isSuccessor(MBB2)) return true;
+ if (MBB2->isSuccessor(MBB1)) return false;
MachineInstr *MBB1I = --MBB1->end();
MachineInstr *MBB2I = --MBB2->end();
- return TII.isCall(MBB2I->getOpcode()) && !TII.isCall(MBB1I->getOpcode());
+ return MBB2I->getDesc().isCall() && !MBB1I->getDesc().isCall();
}
/// OptimizeBlock - Analyze and optimize control flow related to the specified
// last. Only do the swap if one is clearly better to fall through than
// the other.
if (FallThrough == --MBB->getParent()->end() &&
- !IsBetterFallthrough(PriorTBB, MBB, *TII))
+ !IsBetterFallthrough(PriorTBB, MBB))
DoTransform = false;
// We don't want to do this transformation if we have control flow like:
// If this branch is the only thing in its block, see if we can forward
// other blocks across it.
if (CurTBB && CurCond.empty() && CurFBB == 0 &&
- TII->isBranch(MBB->begin()->getOpcode()) && CurTBB != MBB) {
+ MBB->begin()->getDesc().isBranch() && CurTBB != MBB) {
// This block may contain just an unconditional branch. Because there can
// be 'non-branch terminators' in the block, try removing the branch and
// then seeing if the block is empty.