#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/ADT/Statistic.h"
MachineBasicBlock::iterator BBI1);
std::vector<std::pair<unsigned,MachineBasicBlock*> > MergePotentials;
- const MRegisterInfo *RegInfo;
+ const TargetRegisterInfo *RegInfo;
RegScavenger *RS;
// Branch optzn.
bool OptimizeBranches(MachineFunction &MF);
MachineBasicBlock::iterator E) {
unsigned Time = 0;
for (; I != E; ++I) {
- const TargetInstrDescriptor *TID = I->getDesc();
- if (TID->isCall())
+ const TargetInstrDesc &TID = I->getDesc();
+ if (TID.isCall())
Time += 10;
- else if (TID->isSimpleLoad() || TID->mayStore())
+ else if (TID.isSimpleLoad() || TID.mayStore())
Time += 2;
else
++Time;
} else if (FBB) {
if (TBB!=IBB && FBB!=IBB) // cbr then ubr
continue;
- } else if (Cond.size() == 0) {
+ } else if (Cond.empty()) {
if (TBB!=IBB) // ubr
continue;
} else {
MachineInstr *MBB1I = --MBB1->end();
MachineInstr *MBB2I = --MBB2->end();
- return MBB2I->getDesc()->isCall() && !MBB1I->getDesc()->isCall();
+ return MBB2I->getDesc().isCall() && !MBB1I->getDesc().isCall();
}
/// OptimizeBlock - Analyze and optimize control flow related to the specified
// If this branch is the only thing in its block, see if we can forward
// other blocks across it.
if (CurTBB && CurCond.empty() && CurFBB == 0 &&
- MBB->begin()->getDesc()->isBranch() && CurTBB != MBB) {
+ MBB->begin()->getDesc().isBranch() && CurTBB != MBB) {
// This block may contain just an unconditional branch. Because there can
// be 'non-branch terminators' in the block, try removing the branch and
// then seeing if the block is empty.