RS = RegInfo->requiresRegisterScavenging(MF) ? new RegScavenger() : NULL;
- MMI = getAnalysisToUpdate<MachineModuleInfo>();
+ MMI = getAnalysisIfAvailable<MachineModuleInfo>();
bool MadeChangeThisIteration = true;
while (MadeChangeThisIteration) {
const TargetInstrDesc &TID = I->getDesc();
if (TID.isCall())
Time += 10;
- else if (TID.isSimpleLoad() || TID.mayStore())
+ else if (TID.mayLoad() || TID.mayStore())
Time += 2;
else
++Time;
#ifndef _GLIBCXX_DEBUG
assert(0 && "Predecessor appears twice");
#endif
- return(false);
+ return false;
}
}
unsigned minCommonTailLength = (SuccBB ? 1 : 2) + 1;
MadeChange = false;
- DOUT << "\nTryMergeBlocks " << MergePotentials.size();
+ DOUT << "\nTryMergeBlocks " << MergePotentials.size() << '\n';
// Sort by hash value so that blocks with identical end sequences sort
// together.