SelectionDAGBuilder: style fixes (add space between end parentheses and open brace)

[oota-llvm.git] / lib / CodeGen / DFAPacketizer.cpp

diff --git a/lib/CodeGen/DFAPacketizer.cpp b/lib/CodeGen/DFAPacketizer.cpp
index 1a8bcf6a6e838f95a39f94bdbeb2ed74e22e3b1e..840a10128daf41c8113457074e405426ab86b3e3 100644 (file)
--- a/lib/CodeGen/DFAPacketizer.cpp
+++ b/lib/CodeGen/DFAPacketizer.cpp
@@ -23,12 +23,12 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "llvm/CodeGen/ScheduleDAGInstrs.h"
 #include "llvm/CodeGen/DFAPacketizer.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineInstrBundle.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/ScheduleDAGInstrs.h"
 #include "llvm/MC/MCInstrItineraries.h"
+#include "llvm/Target/TargetInstrInfo.h"
 using namespace llvm;
 
 DFAPacketizer::DFAPacketizer(const InstrItineraryData *I, const int (*SIT)[2],
@@ -162,10 +162,8 @@ void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB,
   VLIWScheduler->startBlock(MBB);
   VLIWScheduler->enterRegion(MBB, BeginItr, EndItr, MBB->size());
   VLIWScheduler->schedule();
-  VLIWScheduler->exitRegion();
 
   // Generate MI -> SU map.
-  //std::map <MachineInstr*, SUnit*> MIToSUnit;
   MIToSUnit.clear();
   for (unsigned i = 0, e = VLIWScheduler->SUnits.size(); i != e; ++i) {
     SUnit *SU = &VLIWScheduler->SUnits[i];
@@ -222,4 +220,6 @@ void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB,
 
   // End any packet left behind.
   endPacket(MBB, EndItr);
+  VLIWScheduler->exitRegion();
+  VLIWScheduler->finishBlock();
 }