Make sure we iterate over newly created instructions. Fixes pr13625. Testcase to

[oota-llvm.git] / lib / CodeGen / DFAPacketizer.cpp

diff --git a/lib/CodeGen/DFAPacketizer.cpp b/lib/CodeGen/DFAPacketizer.cpp
index bfbe7790998fd8ebf2fd894c6a1223204413442b..ff2f11353afd04b4a770800490c3fc5c13600678 100644 (file)
--- a/lib/CodeGen/DFAPacketizer.cpp
+++ b/lib/CodeGen/DFAPacketizer.cpp
@@ -116,6 +116,7 @@ DefaultVLIWScheduler::DefaultVLIWScheduler(
   MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
   bool IsPostRA) :
   ScheduleDAGInstrs(MF, MLI, MDT, IsPostRA) {
+  CanHandleTerminators = true;
 }
 
 void DefaultVLIWScheduler::schedule() {
@@ -158,12 +159,11 @@ void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB,
                                       MachineBasicBlock::iterator BeginItr,
                                       MachineBasicBlock::iterator EndItr) {
   assert(VLIWScheduler && "VLIW Scheduler is not initialized!");
+  VLIWScheduler->startBlock(MBB);
   VLIWScheduler->enterRegion(MBB, BeginItr, EndItr, MBB->size());
   VLIWScheduler->schedule();
-  VLIWScheduler->exitRegion();
 
   // Generate MI -> SU map.
-  //std::map <MachineInstr*, SUnit*> MIToSUnit;
   MIToSUnit.clear();
   for (unsigned i = 0, e = VLIWScheduler->SUnits.size(); i != e; ++i) {
     SUnit *SU = &VLIWScheduler->SUnits[i];
@@ -220,4 +220,6 @@ void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB,
 
   // End any packet left behind.
   endPacket(MBB, EndItr);
+  VLIWScheduler->exitRegion();
+  VLIWScheduler->finishBlock();
 }