MachineBasicBlock *BB;
MachineBasicBlock *TrueBB;
MachineBasicBlock *FalseBB;
- std::vector<MachineOperand> BrCond;
- std::vector<MachineOperand> Predicate;
+ SmallVector<MachineOperand, 4> BrCond;
+ SmallVector<MachineOperand, 4> Predicate;
BBInfo() : IsDone(false), IsBeingAnalyzed(false),
IsAnalyzed(false), IsEnqueued(false), IsBrAnalyzable(false),
HasFallThrough(false), IsUnpredicable(false),
bool MadeChange;
public:
static char ID;
- IfConverter() : MachineFunctionPass((intptr_t)&ID) {}
+ IfConverter() : MachineFunctionPass(&ID) {}
virtual bool runOnMachineFunction(MachineFunction &MF);
virtual const char *getPassName() const { return "If Converter"; }
void ScanInstructions(BBInfo &BBI);
BBInfo &AnalyzeBlock(MachineBasicBlock *BB,
std::vector<IfcvtToken*> &Tokens);
- bool FeasibilityAnalysis(BBInfo &BBI, std::vector<MachineOperand> &Cond,
+ bool FeasibilityAnalysis(BBInfo &BBI, SmallVectorImpl<MachineOperand> &Cond,
bool isTriangle = false, bool RevBranch = false);
bool AnalyzeBlocks(MachineFunction &MF,
std::vector<IfcvtToken*> &Tokens);
unsigned NumDups1, unsigned NumDups2);
void PredicateBlock(BBInfo &BBI,
MachineBasicBlock::iterator E,
- std::vector<MachineOperand> &Cond);
+ SmallVectorImpl<MachineOperand> &Cond);
void CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
- std::vector<MachineOperand> &Cond,
+ SmallVectorImpl<MachineOperand> &Cond,
bool IgnoreBr = false);
void MergeBlocks(BBInfo &ToBBI, BBInfo &FromBBI);
Tokens.pop_back();
BBInfo &BBI = Token->BBI;
IfcvtKind Kind = Token->Kind;
+ unsigned NumDups = Token->NumDups;
+ unsigned NumDups2 = Token->NumDups2;
+
+ delete Token;
// If the block has been evicted out of the queue or it has already been
// marked dead (due to it being predicated), then skip it.
DOUT << "Ifcvt (Diamond): BB#" << BBI.BB->getNumber() << " (T:"
<< BBI.TrueBB->getNumber() << ",F:"
<< BBI.FalseBB->getNumber() << ") ";
- RetVal = IfConvertDiamond(BBI, Kind, Token->NumDups, Token->NumDups2);
+ RetVal = IfConvertDiamond(BBI, Kind, NumDups, NumDups2);
DOUT << (RetVal ? "succeeded!" : "failed!") << "\n";
if (RetVal) NumDiamonds++;
break;
/// FeasibilityAnalysis - Determine if the block is a suitable candidate to be
/// predicated by the specified predicate.
bool IfConverter::FeasibilityAnalysis(BBInfo &BBI,
- std::vector<MachineOperand> &Pred,
+ SmallVectorImpl<MachineOperand> &Pred,
bool isTriangle, bool RevBranch) {
// If the block is dead or unpredicable, then it cannot be predicated.
if (BBI.IsDone || BBI.IsUnpredicable)
return false;
// Test predicate subsumsion.
- std::vector<MachineOperand> RevPred(Pred);
- std::vector<MachineOperand> Cond(BBI.BrCond);
+ SmallVector<MachineOperand, 4> RevPred(Pred.begin(), Pred.end());
+ SmallVector<MachineOperand, 4> Cond(BBI.BrCond.begin(), BBI.BrCond.end());
if (RevBranch) {
if (TII->ReverseBranchCondition(Cond))
return false;
return BBI;
}
- std::vector<MachineOperand> RevCond(BBI.BrCond);
+ SmallVector<MachineOperand, 4> RevCond(BBI.BrCond.begin(), BBI.BrCond.end());
bool CanRevCond = !TII->ReverseBranchCondition(RevCond);
unsigned Dups = 0;
///
static void InsertUncondBranch(MachineBasicBlock *BB, MachineBasicBlock *ToBB,
const TargetInstrInfo *TII) {
- std::vector<MachineOperand> NoCond;
+ SmallVector<MachineOperand, 0> NoCond;
TII->InsertBranch(*BB, ToBB, NULL, NoCond);
}
/// successors.
void IfConverter::RemoveExtraEdges(BBInfo &BBI) {
MachineBasicBlock *TBB = NULL, *FBB = NULL;
- std::vector<MachineOperand> Cond;
+ SmallVector<MachineOperand, 4> Cond;
if (!TII->AnalyzeBranch(*BBI.BB, TBB, FBB, Cond))
BBI.BB->CorrectExtraCFGEdges(TBB, FBB, !Cond.empty());
}
BBInfo *CvtBBI = &TrueBBI;
BBInfo *NextBBI = &FalseBBI;
- std::vector<MachineOperand> Cond(BBI.BrCond);
+ SmallVector<MachineOperand, 4> Cond(BBI.BrCond.begin(), BBI.BrCond.end());
if (Kind == ICSimpleFalse)
std::swap(CvtBBI, NextBBI);
}
if (Kind == ICSimpleFalse)
- TII->ReverseBranchCondition(Cond);
+ if (TII->ReverseBranchCondition(Cond))
+ assert(false && "Unable to reverse branch condition!");
if (CvtBBI->BB->pred_size() > 1) {
BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
BBInfo *CvtBBI = &TrueBBI;
BBInfo *NextBBI = &FalseBBI;
- std::vector<MachineOperand> Cond(BBI.BrCond);
+ SmallVector<MachineOperand, 4> Cond(BBI.BrCond.begin(), BBI.BrCond.end());
if (Kind == ICTriangleFalse || Kind == ICTriangleFRev)
std::swap(CvtBBI, NextBBI);
}
if (Kind == ICTriangleFalse || Kind == ICTriangleFRev)
- TII->ReverseBranchCondition(Cond);
+ if (TII->ReverseBranchCondition(Cond))
+ assert(false && "Unable to reverse branch condition!");
if (Kind == ICTriangleRev || Kind == ICTriangleFRev) {
- ReverseBranchCondition(*CvtBBI);
- // BB has been changed, modify its predecessors (except for this
- // one) so they don't get ifcvt'ed based on bad intel.
- for (MachineBasicBlock::pred_iterator PI = CvtBBI->BB->pred_begin(),
- E = CvtBBI->BB->pred_end(); PI != E; ++PI) {
- MachineBasicBlock *PBB = *PI;
- if (PBB == BBI.BB)
- continue;
- BBInfo &PBBI = BBAnalysis[PBB->getNumber()];
- if (PBBI.IsEnqueued) {
- PBBI.IsAnalyzed = false;
- PBBI.IsEnqueued = false;
+ if (ReverseBranchCondition(*CvtBBI)) {
+ // BB has been changed, modify its predecessors (except for this
+ // one) so they don't get ifcvt'ed based on bad intel.
+ for (MachineBasicBlock::pred_iterator PI = CvtBBI->BB->pred_begin(),
+ E = CvtBBI->BB->pred_end(); PI != E; ++PI) {
+ MachineBasicBlock *PBB = *PI;
+ if (PBB == BBI.BB)
+ continue;
+ BBInfo &PBBI = BBAnalysis[PBB->getNumber()];
+ if (PBBI.IsEnqueued) {
+ PBBI.IsAnalyzed = false;
+ PBBI.IsEnqueued = false;
+ }
}
}
}
// If 'true' block has a 'false' successor, add an exit branch to it.
if (HasEarlyExit) {
- std::vector<MachineOperand> RevCond(CvtBBI->BrCond);
+ SmallVector<MachineOperand, 4> RevCond(CvtBBI->BrCond.begin(),
+ CvtBBI->BrCond.end());
if (TII->ReverseBranchCondition(RevCond))
assert(false && "Unable to reverse branch condition!");
TII->InsertBranch(*BBI.BB, CvtBBI->FalseBB, NULL, RevCond);
// block would clobber the predicate, in that case, do the opposite.
BBInfo *BBI1 = &TrueBBI;
BBInfo *BBI2 = &FalseBBI;
- std::vector<MachineOperand> RevCond(BBI.BrCond);
- TII->ReverseBranchCondition(RevCond);
- std::vector<MachineOperand> *Cond1 = &BBI.BrCond;
- std::vector<MachineOperand> *Cond2 = &RevCond;
+ SmallVector<MachineOperand, 4> RevCond(BBI.BrCond.begin(), BBI.BrCond.end());
+ if (TII->ReverseBranchCondition(RevCond))
+ assert(false && "Unable to reverse branch condition!");
+ SmallVector<MachineOperand, 4> *Cond1 = &BBI.BrCond;
+ SmallVector<MachineOperand, 4> *Cond2 = &RevCond;
// Figure out the more profitable ordering.
bool DoSwap = false;
/// specified end with the specified condition.
void IfConverter::PredicateBlock(BBInfo &BBI,
MachineBasicBlock::iterator E,
- std::vector<MachineOperand> &Cond) {
+ SmallVectorImpl<MachineOperand> &Cond) {
for (MachineBasicBlock::iterator I = BBI.BB->begin(); I != E; ++I) {
if (TII->isPredicated(I))
continue;
/// CopyAndPredicateBlock - Copy and predicate instructions from source BB to
/// the destination block. Skip end of block branches if IgnoreBr is true.
void IfConverter::CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
- std::vector<MachineOperand> &Cond,
+ SmallVectorImpl<MachineOperand> &Cond,
bool IgnoreBr) {
+ MachineFunction &MF = *ToBBI.BB->getParent();
+
for (MachineBasicBlock::iterator I = FromBBI.BB->begin(),
E = FromBBI.BB->end(); I != E; ++I) {
const TargetInstrDesc &TID = I->getDesc();
if (IgnoreBr && !isPredicated && TID.isBranch())
break;
- MachineInstr *MI = I->clone();
+ MachineInstr *MI = MF.CloneMachineInstr(I);
ToBBI.BB->insert(ToBBI.BB->end(), MI);
ToBBI.NonPredSize++;
projects / oota-llvm.git / blobdiff