const MachineBranchProbabilityInfo *MBPI;
MachineRegisterInfo *MRI;
+ LiveRegUnits Redefs;
+ LiveRegUnits DontKill;
+
bool PreRegAlloc;
bool MadeChange;
int FnNum;
void PredicateBlock(BBInfo &BBI,
MachineBasicBlock::iterator E,
SmallVectorImpl<MachineOperand> &Cond,
- LiveRegUnits &Redefs,
SmallSet<unsigned, 4> *LaterRedefs = 0);
void CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
SmallVectorImpl<MachineOperand> &Cond,
- LiveRegUnits &Redefs,
- const LiveRegUnits *DontKill = 0,
bool IgnoreBr = false);
void MergeBlocks(BBInfo &ToBBI, BBInfo &FromBBI, bool AddEdges = true);
unsigned Reg = Ops->getReg();
if (Reg == 0)
continue;
- Redefs.RemoveReg(Reg, *TRI);
+ Redefs.removeReg(Reg, *TRI);
}
for (MIBundleOperands Ops(MI); Ops.isValid(); ++Ops) {
if (!Ops->isReg() || !Ops->isDef())
continue;
unsigned Reg = Ops->getReg();
- if (Reg == 0 || Redefs.Contains(Reg, *TRI))
+ if (Reg == 0 || Redefs.contains(Reg, *TRI))
continue;
- Redefs.AddReg(Reg, *TRI);
+ Redefs.addReg(Reg, *TRI);
MachineOperand &Op = *Ops;
MachineInstr *MI = Op.getParent();
for (MIBundleOperands O(&MI); O.isValid(); ++O) {
if (!O->isReg() || !O->isKill())
continue;
- if (DontKill.Contains(O->getReg(), MCRI))
+ if (DontKill.contains(O->getReg(), MCRI))
O->setIsKill(false);
}
}
// Initialize liveins to the first BB. These are potentiall redefined by
// predicated instructions.
- LiveRegUnits Redefs;
- Redefs.AddLiveIns(*(CvtBBI->BB), *TRI);
- Redefs.AddLiveIns(*(NextBBI->BB), *TRI);
+ Redefs.init(TRI);
+ Redefs.addLiveIns(CvtBBI->BB, *TRI);
+ Redefs.addLiveIns(NextBBI->BB, *TRI);
// Compute a set of registers which must not be killed by instructions in
// BB1: This is everything live-in to BB2.
- LiveRegUnits DontKill;
- DontKill.AddLiveIns(*(NextBBI->BB), *TRI);
+ DontKill.init(TRI);
+ DontKill.addLiveIns(NextBBI->BB, *TRI);
if (CvtBBI->BB->pred_size() > 1) {
BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
// Copy instructions in the true block, predicate them, and add them to
// the entry block.
- CopyAndPredicateBlock(BBI, *CvtBBI, Cond, Redefs, &DontKill);
+ CopyAndPredicateBlock(BBI, *CvtBBI, Cond);
// RemoveExtraEdges won't work if the block has an unanalyzable branch, so
// explicitly remove CvtBBI as a successor.
BBI.BB->removeSuccessor(CvtBBI->BB);
} else {
RemoveKills(CvtBBI->BB->begin(), CvtBBI->BB->end(), DontKill, *TRI);
- PredicateBlock(*CvtBBI, CvtBBI->BB->end(), Cond, Redefs);
+ PredicateBlock(*CvtBBI, CvtBBI->BB->end(), Cond);
// Merge converted block into entry block.
BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
// Initialize liveins to the first BB. These are potentially redefined by
// predicated instructions.
- LiveRegUnits Redefs;
- Redefs.AddLiveIns(*(CvtBBI->BB), *TRI);
- Redefs.AddLiveIns(*(NextBBI->BB), *TRI);
+ Redefs.init(TRI);
+ Redefs.addLiveIns(CvtBBI->BB, *TRI);
+ Redefs.addLiveIns(NextBBI->BB, *TRI);
+
+ DontKill.clear();
bool HasEarlyExit = CvtBBI->FalseBB != NULL;
if (CvtBBI->BB->pred_size() > 1) {
BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
// Copy instructions in the true block, predicate them, and add them to
// the entry block.
- CopyAndPredicateBlock(BBI, *CvtBBI, Cond, Redefs, 0, true);
+ CopyAndPredicateBlock(BBI, *CvtBBI, Cond, true);
// RemoveExtraEdges won't work if the block has an unanalyzable branch, so
// explicitly remove CvtBBI as a successor.
} else {
// Predicate the 'true' block after removing its branch.
CvtBBI->NonPredSize -= TII->RemoveBranch(*CvtBBI->BB);
- PredicateBlock(*CvtBBI, CvtBBI->BB->end(), Cond, Redefs);
+ PredicateBlock(*CvtBBI, CvtBBI->BB->end(), Cond);
// Now merge the entry of the triangle with the true block.
BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
// Initialize liveins to the first BB. These are potentially redefined by
// predicated instructions.
- LiveRegUnits Redefs;
- Redefs.AddLiveIns(*(BBI1->BB), *TRI);
+ Redefs.init(TRI);
+ Redefs.addLiveIns(BBI1->BB, *TRI);
// Remove the duplicated instructions at the beginnings of both paths.
MachineBasicBlock::iterator DI1 = BBI1->BB->begin();
// Compute a set of registers which must not be killed by instructions in BB1:
// This is everything used+live in BB2 after the duplicated instructions. We
// can compute this set by simulating liveness backwards from the end of BB2.
- LiveRegUnits DontKill;
- for (MachineBasicBlock::reverse_instr_iterator I = BBI2->BB->rbegin(),
- E = MachineBasicBlock::reverse_instr_iterator(&*DI2); I != E; ++I) {
- DontKill.StepBackward(*I, *TRI);
+ DontKill.init(TRI);
+ for (MachineBasicBlock::reverse_iterator I = BBI2->BB->rbegin(),
+ E = MachineBasicBlock::reverse_iterator(DI2); I != E; ++I) {
+ DontKill.stepBackward(*I, *TRI);
}
for (MachineBasicBlock::const_iterator I = BBI1->BB->begin(), E = DI1; I != E;
++I) {
- Redefs.StepForward(*I, *TRI);
+ Redefs.stepForward(*I, *TRI);
}
BBI.BB->splice(BBI.BB->end(), BBI1->BB, BBI1->BB->begin(), DI1);
BBI2->BB->erase(BBI2->BB->begin(), DI2);
}
// Predicate the 'true' block.
- PredicateBlock(*BBI1, BBI1->BB->end(), *Cond1, Redefs, &RedefsByFalse);
+ PredicateBlock(*BBI1, BBI1->BB->end(), *Cond1, &RedefsByFalse);
// Predicate the 'false' block.
- PredicateBlock(*BBI2, DI2, *Cond2, Redefs);
+ PredicateBlock(*BBI2, DI2, *Cond2);
// Merge the true block into the entry of the diamond.
MergeBlocks(BBI, *BBI1, TailBB == 0);
void IfConverter::PredicateBlock(BBInfo &BBI,
MachineBasicBlock::iterator E,
SmallVectorImpl<MachineOperand> &Cond,
- LiveRegUnits &Redefs,
SmallSet<unsigned, 4> *LaterRedefs) {
bool AnyUnpred = false;
bool MaySpec = LaterRedefs != 0;
/// the destination block. Skip end of block branches if IgnoreBr is true.
void IfConverter::CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
SmallVectorImpl<MachineOperand> &Cond,
- LiveRegUnits &Redefs,
- const LiveRegUnits *DontKill,
bool IgnoreBr) {
MachineFunction &MF = *ToBBI.BB->getParent();
UpdatePredRedefs(MI, Redefs, TRI);
// Some kill flags may not be correct anymore.
- if (DontKill != 0)
- RemoveKills(*MI, *DontKill, *TRI);
+ if (!DontKill.empty())
+ RemoveKills(*MI, DontKill, *TRI);
}
if (!IgnoreBr) {
projects / oota-llvm.git / blobdiff